forked from Lephenixnoir/gint
Lephe
2fd4238d31
This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
224 lines
5.6 KiB
ArmAsm
224 lines
5.6 KiB
ArmAsm
/*
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** gint:core:inth - Interrupt handlers
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** This file only contains the entry points because the gates are managed
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** by device drivers. Each driver will supply its own interrupt handler
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** blocks depending on its configuration.
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*/
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.global _gint_inth_7305
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#ifdef FX9860G
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.global _gint_inth_7705
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#endif
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.global _gint_inth_callback
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.section .gint.blocks, "ax"
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.align 4
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/* Interrupt handlers
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The .gint.blocks section consists of blocks of 32 bytes intended for mapping
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into the VBR space (exception, TLB miss, and interrupt handlers). Each event
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gate is linearly associated with a block number:
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block_id = (event_code - 0x380) / 0x20
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This file provides entry points; drivers may provide their own interrupt
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handlers, and store them in the .gint.blocks section for consistency. They
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should be aware of the consequences of reordering the blocks into the VBR
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space:
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- It is possible to map MPU-specific blocks at runtime, to avoid checking
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the MPU each time an interrupt is handled;
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- However, the blocks can only rely on relative displacements or cross-
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references if their relative order is known and heeded for. A good example
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of this is the timer driver. Please be careful. */
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/* SH7305-TYPE DEBUG INTERRUPT HANDLER - 26 BYTES */
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#if 0
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_gint_inth_7305:
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mov.l 1f, r0
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mov.l @r0, r4
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sts.l pr, @-r15
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mov.l 2f, r0
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jsr @r0
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nop
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lds.l @r15+, pr
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rte
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nop
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.zero 6
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2: .long _debug
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1: .long 0xff000028
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#endif
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/* SH7305-TYPE INTERRUPT HANDLER ENTRY - 40 BYTES */
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_gint_inth_7305:
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/* Save caller-saved registers which might currently be in use by the
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interrupted function, as we don't know what the callback will do */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT register */
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mov.l 1f, r0
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mov.l @r0, r0
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/* Interrupt codes start at 0x400 */
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mov #4, r1
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shll8 r1
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sub r1, r0
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/* Add the distance to the first entry and jump as a subroutine */
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add #40, r0
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bsrf r0
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nop
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/* Restore caller-saved registers */
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 24
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1: .long 0xff000028
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#ifdef FX9860G
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/* SH7705-TYPE INTERRUT HANDLER ENTRY - 52 BYTES */
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_gint_inth_7705:
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/* Save caller-saved registers as before */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT2 register */
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mov.l 1f, r0
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mov.l @r0, r0 /* r0 = old_code */
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/* Translate the event code to SH4 format */
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mov.l 2f, r2
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mov #-5, r3
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shld r3, r0 /* r0 = old_code >> 5 */
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add #-32, r0 /* r0 = (old_code - 0x400) >> 5 */
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mov.b @(r0, r2), r0 /* r0 = (new_code - 0x400) >> 5 */
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mov #5, r3
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shld r3, r0 /* r0 = new_code - 0x400 */
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/* Add the distance between nop and the first entry, and jump */
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add #32, r0
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bsrf r0
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nop
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/* Restore saved registers */
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lds.l @r15+, mach
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lds.l @r15+, macl
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 12
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1: .long 0xa4000000 /* INTEVT2 register */
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2: .long _inth_remap
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.section .gint.data
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.align 4
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/* EVENT CODE TRANSLATION TABLE - 96 BYTES */
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_inth_remap:
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.byte 0x00, 0x01, 0x02, 0xfe, 0x34, 0x35, 0x36, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f
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.byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x20, 0x21, 0x22, 0x23, 0x28, 0x28, 0xff, 0x28
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.byte 0x48, 0x48, 0xff, 0x48, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0x31, 0x32, 0x33, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x2d, 0x2d, 0xff, 0xff, 0x2d, 0x2d, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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#endif
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/* CALLBACK HELPER
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This function implements the callback with context saving. It is a general
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function and does not need to reside in VBR space which is block-structured.
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This function saves registers r0_bank...r7_bank, enables interrupts,
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switches back to user bank and executes the callback. It does not save other
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registers (pr/mach/macl/gbr) which are managed by the handler entry. */
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.section .gint.mapped
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/* gint_inth_callback()
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Calls the specified function with the given argument after saving the user
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context, enabling interrupts and going to user bank.
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@r4 Callback function (volatile void * -> int)
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@r5 Argument (volatile void *)
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Returns the return value of the callback (int). */
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_gint_inth_callback:
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stc.l r0_bank, @-r15
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stc.l r1_bank, @-r15
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stc.l r2_bank, @-r15
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stc.l r3_bank, @-r15
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stc.l r4_bank, @-r15
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stc.l r5_bank, @-r15
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stc.l r6_bank, @-r15
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stc.l r7_bank, @-r15
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stc.l spc, @-r15
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stc.l ssr, @-r15
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stc.l sr, @-r15
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/* Enable interrupts and go back to user bank. SR.IMASK is already set
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to the level of the current interrupt, which makes sure we can only
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be re-interrupted by something with a higher priority. */
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mov.l .SR_clear_RB_BL, r1
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stc sr, r0
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and r1, r0
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ldc r0, sr
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/* We are now in the user bank, but we can still use r0..r7 as the
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important values have been saved on the stack. Call back. */
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stc r4_bank, r0
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sts.l pr, @-r15
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jsr @r0
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stc r5_bank, r4
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lds.l @r15+, pr
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/* We want to forward the return value to the system bank */
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ldc r0, r0_bank
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/* Restore the previous status register and the registers of the
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interrupted procedure. */
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ldc.l @r15+, sr
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ldc.l @r15+, ssr
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ldc.l @r15+, spc
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ldc.l @r15+, r7_bank
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ldc.l @r15+, r6_bank
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ldc.l @r15+, r5_bank
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ldc.l @r15+, r4_bank
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ldc.l @r15+, r3_bank
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ldc.l @r15+, r2_bank
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ldc.l @r15+, r1_bank
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rts
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ldc.l @r15+, r0_bank
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.align 4
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.SR_clear_RB_BL:
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.long ~((1 << 29) | (1 << 28))
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