forked from Lephenixnoir/gint
Lephe
2fd4238d31
This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
50 lines
990 B
ArmAsm
50 lines
990 B
ArmAsm
/*
|
|
** gint:core:vbr - Assembler-level VBR management
|
|
*/
|
|
|
|
.global _gint_setvbr
|
|
.section .gint.mapped
|
|
|
|
/* gint_setvbr()
|
|
Changes the VBR address and the calls the configuration function while
|
|
interrupts are disabled. The configuration function must change either the
|
|
priority registers or the interrupt masks, and make sure that all the
|
|
interrupts that it leaves enabled are handled by the new VBR handlers.
|
|
|
|
@r4 vbr New VBR address (uint32_t)
|
|
@r5 configure Configuration function (void -> void)
|
|
Returns the previous VBR address. */
|
|
_gint_setvbr:
|
|
mov.l r9, @-r15
|
|
mov.l r8, @-r15
|
|
sts.l pr, @-r15
|
|
|
|
mov #1, r8
|
|
mov #28, r0
|
|
shld r0, r8
|
|
|
|
/* Block all interrupts */
|
|
stc sr, r0
|
|
or r8, r0
|
|
ldc r0, sr
|
|
|
|
/* Set the new VBR address */
|
|
stc vbr, r9
|
|
ldc r4, vbr
|
|
|
|
/* Call the configuration function */
|
|
jsr @r5
|
|
nop
|
|
|
|
/* Enable interrupts again */
|
|
stc sr, r0
|
|
not r8, r8
|
|
and r8, r0
|
|
ldc r0, sr
|
|
|
|
lds.l @r15+, pr
|
|
mov.l @r15+, r8
|
|
mov r9, r0
|
|
rts
|
|
mov.l @r15+, r9
|