Commit Graph

20 Commits

Author SHA1 Message Date
Lephenixnoir 9d7c87ac3d
fxos: rename Instruction -> OldInstruction 2023-09-24 10:45:40 +02:00
Lephenixnoir a4cda4cb66
fxos: rename Function -> OldFunction
This prepares the introduction of a new program model different enough
from the original that I'd rather build it on the side than
progressively update the current one.
2023-09-03 19:20:45 +02:00
Lephenixnoir 47764a61eb
fxos: refactor AsmInstruction categories into assembly table tags 2023-08-27 23:25:35 +02:00
Lephenixnoir 2dbd910379
fxos, _if: add insufficient call analysis
We look for constants in call instruction parameters, but this only
works for jsr because the register argument in [jmp @rn] is not known to
be a constant yet (some static analysis required).
2023-08-20 20:23:30 +02:00
Lephenixnoir df4bba2c1a
fxos: analyze pcrel in cfg (for future call analysis)
This will not cover advanced stuff that relies on static analysis, but
we don't care at the moment.
2023-08-20 19:42:06 +02:00
Dr-Carlos 12845a1675 Improve command classification 2022-04-15 06:09:18 +09:30
Lephenixnoir 3a9a622ee3
_ic: new command to show claims on addresses 2022-04-06 18:41:41 +01:00
Lephenixnoir ee1c36db4e
_ads: functions now claim the instructions they explore 2022-04-06 12:15:34 +01:00
Lephenixnoir 6ae1a88bf7
_ads: register functions during discovery 2022-04-05 14:02:06 +01:00
Lephenixnoir d7b3fd0de8
add infrastructure for function passes
Ported existing passes to the new pass interface, now working properly.
2022-04-05 11:11:19 +01:00
Lephenixnoir 29cd2815ec
refactor disassembly infrastructure and passes 2022-03-28 20:59:30 +01:00
Lephenixnoir a9660da767
get rid of exceptions in the library, use explicit errors 2022-03-27 13:59:49 +01:00
Lephenixnoir 50963d7c20
refactor logging utility 2022-03-27 12:57:36 +01:00
Lephenixnoir c8b28b447f
masive improvements to memory use by compacting core objects
* Store CpuRegister on a single byte
* Store operation sizes (0, 1, 2, 4) on a single byte
* Share the (disp) and (imm) fields of instruction arguments
* Store instructions as char[12] instead of std::string (>32B)
* Store instruction args in Argument[2], not std::vector (>24B)

Size changes:
  CpuRegister:    4B ->  1B
  Argument:      24B ->  8B
  Instruction:  >64B -> 32B

This reduced the malloc size from 3.3M to 177k after a standard 40-line
disassembly (this excludes OS files mapped to memory), and improved the
loading time for the SH3 instruction table by about 30% (100 ms -> 65
ms).
2021-03-16 13:37:55 +01:00
Lephenixnoir 2e58a8850b
support non-decoded instructions
This finally makes it possible to disassemble any interval without
worrying about potential errors. That's some progress.

By the way, now we can fully disassemble fx@3.10. Takes about 6 seconds
for the analysis passes, and ~9 seconds for printing on my machine.
2020-02-29 16:32:25 +01:00
Lephenixnoir c1c1be2d2c
support for mova, and more responsible OS creation 2020-02-29 11:25:03 +01:00
Lephenixnoir c5a7071dcc better manage exceptions and instruction-level passes 2020-02-28 16:19:50 +01:00
Lephenixnoir 4d9edecad9
start with the analysis passes
-> The cfg pass loads the function into memory, annotates leaders and
   jumps, and resolves delay slots.
-> The pcrel pass currently computes locations for pc-relative moves and
   jumps, but does not yet compute the pc-relative moved data.
-> The print pass displays the results of analysis with various layout
   and formatting options.
2020-02-12 07:53:00 +01:00
Lephenixnoir c499ca1f90 define a library abstraction and logging helpers
-> The Library class handles the loading and parsing of data files. This
   is because any fxos application will use this since everyone will
   have only one library.
-> Add a logging function that automatically format()s everything in
   sight with basic logging levels and a verbose mode. Standard logs are
   prefixed with __func__ for debugging purposes.
-> Allow format() to take std::string arguments for %s by statically
   extracting c_str()s.
-> Add a simple timing utility to understand which file load or
   disassembler pass takes up the time.
2020-01-26 12:48:39 +01:00
Lephenixnoir 468495856d
implement more of the meat of the tool
* Separate OS and Target conceptually; now an OS is created on an
  existing target which must have ROM bound.
* Add a configuration file with a data library and description files
  which are automatically loaded at startup.
* As a first application, implement target descriptions. It is now
  possible (given the proper library) to type [fxos info fx@3.10] to get
  information on the fx OS version 3.10.
* Set up the pass infrastructure and the first few easy passes. This
  is still a Work In Progress and not yet called from the command-line.
* Improve the copy/move behavior of classes (C++ concerns).
* Add instruction metadata, which will make it easier to write actual
  useful analysis passes.
2019-12-28 17:18:13 +01:00