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gint/include/gint/mmu.h

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Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
//---
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
// gint:mmu - Memory Management Unit
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
//---
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
#ifndef GINT_MMU
#define GINT_MMU
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
add C++ header guards
2021-06-13 18:13:09 +02:00
#ifdef __cplusplus
extern "C" {
#endif
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
#include <gint/mpu/mmu.h>
fs: buffer Fugue writes through RAM Writing from ROM causes occasional crashes, which are fairly hard to produce when the buffers are small.
2022-01-10 14:45:01 +01:00
#include <stdbool.h>
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
//---
// Unified interface
//---
/* mmu_translate(): Get the physical address for a virtual page
Looks for a translation with the specified virtual address as start, and
returns the corresponding physical address. Only works if the argument is
page-aligned.
@virtual Virtual page address
mmu: add an mmu_uram_size() function detecting static RAM size This function performs a more rigorous analysis of the mapped region by checking continuity. So far all pages mapped in userpsace have been contiguous, so the results are identical to gint[HWURAM]. Page size is now optionnaly provided in mmu_translate() and its subfunctions; programs that use this function need to add a second NULL parameter.
2021-02-05 18:19:53 +01:00
@size If provided, set to the size of the page
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
Returns the page's physical address, or -1 if not mapped. */
mmu: add an mmu_uram_size() function detecting static RAM size This function performs a more rigorous analysis of the mapped region by checking continuity. So far all pages mapped in userpsace have been contiguous, so the results are identical to gint[HWURAM]. Page size is now optionnaly provided in mmu_translate() and its subfunctions; programs that use this function need to add a second NULL parameter.
2021-02-05 18:19:53 +01:00
uint32_t mmu_translate(uint32_t page, uint32_t *size);
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* mmu_uram(): Get pointer to physical start of user RAM
Returns a pointer to the physical location behind 0x08100000. The physical
location can be used to access without the TLB, which is useful when
interrupts are processed with SR.BL=1. However, the location is highly
platform-dependent. */
void *mmu_uram(void);
mmu: add an mmu_uram_size() function detecting static RAM size This function performs a more rigorous analysis of the mapped region by checking continuity. So far all pages mapped in userpsace have been contiguous, so the results are identical to gint[HWURAM]. Page size is now optionnaly provided in mmu_translate() and its subfunctions; programs that use this function need to add a second NULL parameter.
2021-02-05 18:19:53 +01:00
/* mmu_uram_size(): Get size of user RAM area
Returns the size of the static memory at 0x08100000, whose address is
returned by mmu_uram(). This is typically 8k on SH3 fx-9860G, 32k on SH4
fx-9860G, and 512k on fx-CG 50. */
uint32_t mmu_uram_size(void);
fs: buffer Fugue writes through RAM Writing from ROM causes occasional crashes, which are fairly hard to produce when the buffers are small.
2022-01-10 14:45:01 +01:00
/* mmu_is_rom(): Determine if an address points to ROM
Checks whether the supplied pointer points to ROM or to a virtualized
portion of ROM. For the sake of efficiency, this function uses heuristics
about the structure of P0 rather than actually checking the TLB.
This is useful during filesystem accesses because only data outside of ROM
can be written to files. Pointers for which this function returns true
cannot be used as a source for BFile_Write(). */
bool mmu_is_rom(void const *ptr);
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
//---
// SH7705 TLB
//---
/* tlb_addr() - get the P4 address of a TLB address entry
@way TLB way (0..3)
@E Entry number (0..31)
Returns a pointer to the entry. */
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
tlb_addr_t const *tlb_addr(uint way, uint E);
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
/* tlb_data() - get the P4 address of a TLB data entry
@way TLB way (0..3)
@E Entry number (0..31)
Returns a pointer to the entry. */
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
tlb_data_t const *tlb_data(uint way, uint E);
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
way too much, including bopti/topti, timers, and more.
2019-02-21 20:58:38 +01:00
/* tlb_mapped_memory() - count amount of mapped memory
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
This function returns the amount of mapped text and data segment memory, in
bytes. The ranges are defined as follows:
ROM 00300000:512k
RAM 08100000:512k
Other mappings are ignored. Both pointers may be NULL.
@rom Pointer to amount of mapped ROM
@ram Pointer to amount of mapped RAM */
void tlb_mapped_memory(uint32_t *p_rom, uint32_t *p_ram);
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* tlb_translate(): Get the physical address for a virtual page */
mmu: add an mmu_uram_size() function detecting static RAM size This function performs a more rigorous analysis of the mapped region by checking continuity. So far all pages mapped in userpsace have been contiguous, so the results are identical to gint[HWURAM]. Page size is now optionnaly provided in mmu_translate() and its subfunctions; programs that use this function need to add a second NULL parameter.
2021-02-05 18:19:53 +01:00
uint32_t tlb_translate(uint32_t page, uint32_t *size);
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
//---
// SH7305 Unified TLB
//---
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* utlb_addr() - get the P4 address of a UTLB address entry
@E Entry number (should be in range 0..63)
Returns a pointer to the entry. */
mmu: provide read-only access to ITLB
2023-02-02 14:23:03 +01:00
utlb_addr_t const *utlb_addr(uint E);
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* utlb_data() - get the P4 address of a UTLB data entry
@E Entry number (should be in range 0..63)
Returns a pointer to the entry. */
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
utlb_data_t const *utlb_data(uint E);
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* utlb_mapped_memory() - count amount of mapped memory
This function returns the amount of mapped text and data segment memory, in
bytes. The ranges are defined as follows:
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
ROM 00300000:4M
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
RAM 08100000:512k
Other mappings are ignored. Both pointers may be NULL.
@rom Pointer to amount of mapped ROM
@ram Pointer to amount of mapped RAM */
void utlb_mapped_memory(uint32_t *rom, uint32_t *ram);
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* utlb_translate(): Get the physical address for a virtual page */
mmu: add an mmu_uram_size() function detecting static RAM size This function performs a more rigorous analysis of the mapped region by checking continuity. So far all pages mapped in userpsace have been contiguous, so the results are identical to gint[HWURAM]. Page size is now optionnaly provided in mmu_translate() and its subfunctions; programs that use this function need to add a second NULL parameter.
2021-02-05 18:19:53 +01:00
uint32_t utlb_translate(uint32_t page, uint32_t *size);
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
mmu: provide read-only access to ITLB
2023-02-02 14:23:03 +01:00
/* itlb_addr(): Get the P4 address of an ITLB address entry
@E Entry number (0..3)
Returns a pointer to the entry. */
itlb_addr_t const *itlb_addr(uint E);
/* itlb_data(): Get the P4 address of an ITLB data entry
@E Entry number (0..3)
Returns a pointer to the entry. */
itlb_data_t const *itlb_data(uint E);
add C++ header guards
2021-06-13 18:13:09 +02:00
#ifdef __cplusplus
}
#endif
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
#endif /* GINT_MMU */