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mmu: provide read-only access to ITLB

This commit is contained in:
Lephe 2023-02-02 14:23:03 +01:00
parent a091efc894
commit 1a61e97ef0
Signed by: Lephenixnoir
GPG Key ID: 1BBA026E13FC0495
4 changed files with 55 additions and 11 deletions
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12
include/gint/mmu.h
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@ -89,7 +89,7 @@ uint32_t tlb_translate(uint32_t page, uint32_t *size);
/* utlb_addr() - get the P4 address of a UTLB address entry
@E Entry number (should be in range 0..63)
Returns a pointer to the entry. */
const utlb_addr_t *utlb_addr(uint E);
utlb_addr_t const *utlb_addr(uint E);
/* utlb_data() - get the P4 address of a UTLB data entry
@E Entry number (should be in range 0..63)
@ -110,6 +110,16 @@ void utlb_mapped_memory(uint32_t *rom, uint32_t *ram);
/* utlb_translate(): Get the physical address for a virtual page */
uint32_t utlb_translate(uint32_t page, uint32_t *size);
/* itlb_addr(): Get the P4 address of an ITLB address entry
@E Entry number (0..3)
Returns a pointer to the entry. */
itlb_addr_t const *itlb_addr(uint E);
/* itlb_data(): Get the P4 address of an ITLB data entry
@E Entry number (0..3)
Returns a pointer to the entry. */
itlb_data_t const *itlb_data(uint E);
#ifdef __cplusplus
}
#endif

36
include/gint/mpu/mmu.h
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@ -49,12 +49,10 @@ typedef struct
} GPACKED(4) tlb_data_t;
//---
// SH7305 TLB. Refer to:
// "Renesas SH7724 User's Manual: Hardware"
// Section 7: "Memory Management Unit (MMU)"
// SH7305 TLB. Refer to SH4AL-DSP manual, section 7 (MMU)
//---
/* utlb_addr_t - address part of a UTLB entry */
/* utlb_addr_t: Address part of a UTLB entry */
typedef struct
{
uint VPN :22;
@ -64,7 +62,7 @@ typedef struct
} GPACKED(4) utlb_addr_t;
/* utlb_data_t - data part of a UTLB entry */
/* utlb_data_t: Data part of a UTLB entry */
typedef struct
{
uint :3;
@ -81,6 +79,34 @@ typedef struct
} GPACKED(4) utlb_data_t;
/* itlb_addr_t: Address part of an ITLB entry */
typedef struct
{
uint VPN :22;
uint :1;
uint V :1;
uint ASID :8;
} GPACKED(4) itlb_addr_t;
/* itlb_data_t: Data part of an ITLB entry */
typedef struct
{
uint :3;
uint PPN :19;
uint :1;
uint V :1;
uint SZ1 :1;
uint PR :1;
uint :1;
uint SZ0 :1;
uint C :1;
uint :1;
uint SH :1;
uint :1;
} GPACKED(4) itlb_data_t;
typedef volatile struct
{
lword_union(PTEH,

2
src/kernel/exch.c
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@ -160,7 +160,7 @@ GNORETURN static void gint_default_panic(GUNUSED uint32_t code)
if(code == 0x180)
{
uint16_t *opcodes = (void *)PC;
dprint(6, 141, "Opcodes: %04x %04x [%04x] %04x",
dprint(6, 160, "Opcodes: %04x %04x [%04x] %04x",
opcodes[-2], opcodes[-1], opcodes[0], opcodes[1]);
}
#endif

16
src/mmu/mmu.c
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@ -129,21 +129,18 @@ uint32_t tlb_translate(uint32_t page, uint32_t *size)
// SH7305 Unified TLB
//---
/* utlb_addr() - get the P4 address of a UTLB address entry */
GINLINE const utlb_addr_t *utlb_addr(uint E)
{
uint32_t addr = 0xf6000000 | ((E & 0x3f) << 8);
return (void *)addr;
}
/* utlb_data() - get the P4 address of a UTLB data entry */
GINLINE const utlb_data_t *utlb_data(uint E)
{
uint32_t addr = 0xf7000000 | ((E & 0x3f) << 8);
return (void *)addr;
}
/* utlb_mapped_memory() - count amount of mapped memory */
void utlb_mapped_memory(uint32_t *p_rom, uint32_t *p_ram)
{
uint32_t rom = 0, ram = 0;
@ -170,7 +167,6 @@ void utlb_mapped_memory(uint32_t *p_rom, uint32_t *p_ram)
gint[HWURAM] = ram;
}
/* utlb_translate(): Get the physical address for a virtual page */
uint32_t utlb_translate(uint32_t page, uint32_t *size)
{
for(int E = 0; E < 64; E++)
@ -191,6 +187,18 @@ uint32_t utlb_translate(uint32_t page, uint32_t *size)
return -1;
}
itlb_addr_t const *itlb_addr(uint E)
{
uint32_t addr = 0xf2000000 | ((E & 3) << 8);
return (void *)addr;
}
itlb_data_t const *itlb_data(uint E)
{
uint32_t addr = 0xf3000000 | ((E & 3) << 8);
return (void *)addr;
}
static void configure(void)
{
/* Make writes to the control register area synchronous; this is needed