some cleaning in cpg.c
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1f4fbcec43
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d013bcdd20
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@ -26,8 +26,8 @@ const clock_frequency_t *clock_freq(void)
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// SH7705 Clock signals
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//---
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#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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#define CPG SH7705_CPG
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//#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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//#define CPGSH3 SH7705_CPG
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void sh7705_probe(void)
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{
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@ -41,11 +41,11 @@ void sh7705_probe(void)
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int ckio = xtal * pll2;
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/* This signal is multiplied by the PLL1 circuit */
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int pll1 = CPG.FRQCR.STC + 1;
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int pll1 = SH7705_CPG.FRQCR.STC + 1;
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/* Iphi and Pphi have dividers (Bphi is always equal to CKIO) */
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int idiv = CPG.FRQCR.IFC;
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int pdiv = CPG.FRQCR.PFC;
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int idiv = SH7705_CPG.FRQCR.IFC;
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int pdiv = SH7705_CPG.FRQCR.PFC;
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/* Fill in the setting structure */
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freq.PLL1 = pll1;
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@ -69,33 +69,33 @@ void sh7705_probe(void)
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freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
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}
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#undef CPG
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#endif /* FX9860G and platform-agnostic */
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//#undef CPG
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//#endif /* FX9860G and platform-agnostic */
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//---
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// SH7305 clock signals
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//---
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#define CPG SH7305_CPG
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//#define CPGSH4 SH7305_CPG
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static void sh7305_probe(void)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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int pll = SH7305_CPG.FRQCR.STC + 1;
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freq.PLL = pll;
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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int fll = SH7305_CPG.FLLFRQ.FLF;
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if(SH7305_CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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freq.FLL = fll;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divp = CPG.FRQCR.P1FC;
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int divb = SH7305_CPG.FRQCR.BFC;
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int divi = SH7305_CPG.FRQCR.IFC;
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int divp = SH7305_CPG.FRQCR.P1FC;
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freq.Bphi_div = 1 << (divb + 1);
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freq.Iphi_div = 1 << (divi + 1);
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@ -103,8 +103,8 @@ static void sh7305_probe(void)
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/* Deduce the input frequency of divider 1 */
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int base = 32768;
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if(CPG.PLLCR.FLLE) base *= fll;
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if(CPG.PLLCR.PLLE) base *= pll;
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if(SH7305_CPG.PLLCR.FLLE) base *= fll;
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if(SH7305_CPG.PLLCR.PLLE) base *= pll;
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/* And the frequency of all other input clocks */
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freq.RTCCLK_f = 32768;
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@ -113,7 +113,7 @@ static void sh7305_probe(void)
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freq.Pphi_f = base >> (divp + 1);
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}
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#undef CPG
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//#undef CPG
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//---
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@ -124,10 +124,14 @@ void cpg_compute_freq(void)
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{
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/* This avoids warnings about sh7705_probe() being undefined when
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building for fxcg50 */
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/*
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#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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isSH3() ? sh7705_probe() :
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#endif
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sh7305_probe();
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*/
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isSH3() ? sh7705_probe() : sh7305_probe();
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}
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static void configure(void)
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@ -16,12 +16,14 @@
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/wdt.h>
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/*
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define CPGSH3 SH7705_CPG
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#define BSCSH3 SH7705_BSC
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#define WDTSH3 SH7705_WDT
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#define SH7705_CPG SH7705_CPG
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#define SH7705_BSC SH7705_BSC
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#define SH7705_WDT SH7705_WDT
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*/
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//---
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// Low-level clock speed access
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@ -62,31 +64,31 @@ void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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if(isSH3())
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{
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s->FLLFRQ = 0xFFFFFFF; // not used for SH3 MPUs
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s->FRQCR = CPGSH3.FRQCR.word;
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s->FRQCR = (uint32_t) SH7705_CPG.FRQCR.word;
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s->CS0BCR = BSCSH3.CS0BCR.lword;
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s->CS0WCR = BSCSH3.CS0WCR.lword;
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s->CS2BCR = BSCSH3.CS2BCR.lword;
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s->CS2WCR = BSCSH3.CS2WCR.lword;
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s->CS3BCR = BSCSH3.CS3BCR.lword;
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s->CS3WCR = BSCSH3.CS3WCR.lword;
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s->CS5aBCR = BSCSH3.CS5ABCR.lword;
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s->CS5aWCR = BSCSH3.CS5AWCR.lword;
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s->CS0BCR = SH7705_BSC.CS0BCR.lword;
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s->CS0WCR = SH7705_BSC.CS0WCR.lword;
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s->CS2BCR = SH7705_BSC.CS2BCR.lword;
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s->CS2WCR = SH7705_BSC.CS2WCR.lword;
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s->CS3BCR = SH7705_BSC.CS3BCR.lword;
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s->CS3WCR = SH7705_BSC.CS3WCR.lword;
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s->CS5aBCR = SH7705_BSC.CS5ABCR.lword;
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s->CS5aWCR = SH7705_BSC.CS5AWCR.lword;
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}
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if(isSH4())
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{
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s->FLLFRQ = CPG.FLLFRQ.lword;
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s->FRQCR = CPG.FRQCR.lword;
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s->FLLFRQ = SH7305_CPG.FLLFRQ.lword;
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s->FRQCR = SH7305_CPG.FRQCR.lword;
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s->CS0BCR = BSC.CS0BCR.lword;
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s->CS0WCR = BSC.CS0WCR.lword;
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s->CS2BCR = BSC.CS2BCR.lword;
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s->CS2WCR = BSC.CS2WCR.lword;
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s->CS3BCR = BSC.CS3BCR.lword;
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s->CS3WCR = BSC.CS3WCR.lword;
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s->CS5aBCR = BSC.CS5ABCR.lword;
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s->CS5aWCR = BSC.CS5AWCR.lword;
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s->CS0BCR = SH7305_BSC.CS0BCR.lword;
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s->CS0WCR = SH7305_BSC.CS0WCR.lword;
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s->CS2BCR = SH7305_BSC.CS2BCR.lword;
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s->CS2WCR = SH7305_BSC.CS2WCR.lword;
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s->CS3BCR = SH7305_BSC.CS3BCR.lword;
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s->CS3WCR = SH7305_BSC.CS3WCR.lword;
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s->CS5aBCR = SH7305_BSC.CS5ABCR.lword;
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s->CS5aWCR = SH7305_BSC.CS5AWCR.lword;
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}
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return;
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@ -96,42 +98,42 @@ void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(isSH3())
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{
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WDTSH3.WTCNT.WRITE = 0;
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WDTSH3.WTCNT.WRITE = 0x65;
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CPGSH3.FRQCR.word = 0x1000 | s->FRQCR;
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BSCSH3.CS0BCR.lword = s->CS0BCR;
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BSCSH3.CS0WCR.lword = s->CS0WCR;
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BSCSH3.CS2BCR.lword = s->CS2BCR;
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BSCSH3.CS2WCR.lword = s->CS2WCR;
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BSCSH3.CS3BCR.lword = s->CS3BCR;
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BSCSH3.CS3WCR.lword = s->CS3WCR;
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BSCSH3.CS5ABCR.lword = s->CS5aBCR;
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BSCSH3.CS5AWCR.lword = s->CS5aWCR;
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SH7705_WDT.WTCNT.WRITE = 0;
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SH7705_WDT.WTCNT.WRITE = 0x65;
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SH7705_CPG.FRQCR.word = 0x1000 | (uint16_t) s->FRQCR;
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SH7705_BSC.CS0BCR.lword = s->CS0BCR;
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SH7705_BSC.CS0WCR.lword = s->CS0WCR;
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SH7705_BSC.CS2BCR.lword = s->CS2BCR;
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SH7705_BSC.CS2WCR.lword = s->CS2WCR;
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SH7705_BSC.CS3BCR.lword = s->CS3BCR;
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SH7705_BSC.CS3WCR.lword = s->CS3WCR;
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SH7705_BSC.CS5ABCR.lword = s->CS5aBCR;
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SH7705_BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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if(isSH4())
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{
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BSC.CS0WCR.WR = 11; /* 18 cycles */
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SH7305_BSC.CS0WCR.WR = 11; /* 18 cycles */
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CPG.FLLFRQ.lword = s->FLLFRQ;
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CPG.FRQCR.lword = s->FRQCR;
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CPG.FRQCR.KICK = 1;
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while(CPG.LSTATS != 0) {}
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SH7305_CPG.FLLFRQ.lword = s->FLLFRQ;
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SH7305_CPG.FRQCR.lword = s->FRQCR;
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SH7305_CPG.FRQCR.KICK = 1;
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while(SH7305_CPG.LSTATS != 0) {}
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BSC.CS0BCR.lword = s->CS0BCR;
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BSC.CS0WCR.lword = s->CS0WCR;
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BSC.CS2BCR.lword = s->CS2BCR;
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BSC.CS2WCR.lword = s->CS2WCR;
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BSC.CS3BCR.lword = s->CS3BCR;
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BSC.CS3WCR.lword = s->CS3WCR;
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SH7305_BSC.CS0BCR.lword = s->CS0BCR;
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SH7305_BSC.CS0WCR.lword = s->CS0WCR;
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SH7305_BSC.CS2BCR.lword = s->CS2BCR;
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SH7305_BSC.CS2WCR.lword = s->CS2WCR;
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SH7305_BSC.CS3BCR.lword = s->CS3BCR;
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SH7305_BSC.CS3WCR.lword = s->CS3WCR;
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if(BSC.CS3WCR.A3CL == 1)
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if(SH7305_BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = s->CS5aBCR;
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BSC.CS5AWCR.lword = s->CS5aWCR;
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SH7305_BSC.CS5ABCR.lword = s->CS5aBCR;
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SH7305_BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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return;
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@ -255,7 +257,6 @@ static struct cpg_overclock_setting settings_prizm[5] = {
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.CS5aWCR = 0x00010240 },
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};
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/*settings for the fx9860G SH3 based*/
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static struct cpg_overclock_setting settings_fx9860g_sh3[5] = {
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/* CLOCK_SPEED_F1 */
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@ -459,15 +460,15 @@ int clock_get_speed(void)
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for(int i = 0; i < 5; i++) {
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struct cpg_overclock_setting *s = &settings[i];
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if(CPGSH3.FRQCR.word == s->FRQCR // FRQCR is a uint16_t for SH3
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&& BSCSH3.CS0BCR.lword == s->CS0BCR
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&& BSCSH3.CS2BCR.lword == s->CS2BCR
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&& BSCSH3.CS3BCR.lword == s->CS3BCR
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&& BSCSH3.CS5ABCR.lword == s->CS5aBCR
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&& BSCSH3.CS0WCR.lword == s->CS0WCR
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&& BSCSH3.CS2WCR.lword == s->CS2WCR
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&& BSCSH3.CS3WCR.lword == s->CS3WCR
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&& BSCSH3.CS5AWCR.lword == s->CS5aWCR)
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if(SH7705_CPG.FRQCR.word == (uint16_t) s->FRQCR // FRQCR is a uint16_t for SH3
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&& SH7705_BSC.CS0BCR.lword == s->CS0BCR
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&& SH7705_BSC.CS2BCR.lword == s->CS2BCR
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&& SH7705_BSC.CS3BCR.lword == s->CS3BCR
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&& SH7705_BSC.CS5ABCR.lword == s->CS5aBCR
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&& SH7705_BSC.CS0WCR.lword == s->CS0WCR
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&& SH7705_BSC.CS2WCR.lword == s->CS2WCR
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&& SH7705_BSC.CS3WCR.lword == s->CS3WCR
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&& SH7705_BSC.CS5AWCR.lword == s->CS5aWCR)
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return CLOCK_SPEED_F1 + i;
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}
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}
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@ -477,16 +478,16 @@ int clock_get_speed(void)
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for(int i = 0; i < 5; i++) {
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struct cpg_overclock_setting *s = &settings[i];
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if(CPG.FLLFRQ.lword == s->FLLFRQ
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&& CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4
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&& BSC.CS0BCR.lword == s->CS0BCR
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&& BSC.CS2BCR.lword == s->CS2BCR
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&& BSC.CS3BCR.lword == s->CS3BCR
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&& BSC.CS5ABCR.lword == s->CS5aBCR
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&& BSC.CS0WCR.lword == s->CS0WCR
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&& BSC.CS2WCR.lword == s->CS2WCR
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&& BSC.CS3WCR.lword == s->CS3WCR
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&& BSC.CS5AWCR.lword == s->CS5aWCR)
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if(SH7305_CPG.FLLFRQ.lword == s->FLLFRQ
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&& SH7305_CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4
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&& SH7305_BSC.CS0BCR.lword == s->CS0BCR
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&& SH7305_BSC.CS2BCR.lword == s->CS2BCR
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&& SH7305_BSC.CS3BCR.lword == s->CS3BCR
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&& SH7305_BSC.CS5ABCR.lword == s->CS5aBCR
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&& SH7305_BSC.CS0WCR.lword == s->CS0WCR
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&& SH7305_BSC.CS2WCR.lword == s->CS2WCR
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&& SH7305_BSC.CS3WCR.lword == s->CS3WCR
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&& SH7305_BSC.CS5AWCR.lword == s->CS5aWCR)
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return CLOCK_SPEED_F1 + i;
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}
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}
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