Commit Graph

14 Commits

Author SHA1 Message Date
Lephe bf21246f13
kernel: mask interrupts during callbacks on fx-CG Manager
The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means
that we have to mask interrupts as on SH3.
2020-07-20 16:44:27 +02:00
Lephe 0622928f22
rtc: robust interrupt handling and SH3 compatibility
This commit changes the interrupt handler arrangement to support the PRI
interrupt on SH3 (a gap is needed between 0xaa0 and its helper).

It also introduces the use of the _gint_inth_callback function for the
callback, which provides dynamic TLB during the interrupt, and revealed
a bug about IMASK not being set automatically on SH3.

Finally, it sets the interrupt settings of the RTC more conservatively,
by wiping RCR1 and the carry, alarm and periodic interrupt flags during
initialization and context restoration.
2020-07-19 20:06:50 +02:00
Lephe a06213ca11
kernel: mask interrupts during callbacks on SH3!
This change fixes very weird bugs first observed with the RTC, related
to IMASK not being updated when an interrupt occurs to avoid
re-interruption.

On SH4 there is a CPUOPM setting that automatically sets IMASK to the
level of the accepted interrupt, which is so exactly what every kernel
needs that I can't figure out why this isn't the only behavior.

Turns out on SH3 it's not even an option. This commit sets IMASK to 15
when accepting a callback on SH3. This most notably prevents the gray
engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
Lephe 2751dcf045
remove the .gint.data section
Since both platforms now have their VBR and gint-specific data loaded
along the add-in's data, the .gint.data section is entirely unused.

The .gint.bss section is still used for uninitialized objects (it has
different semantics than .bss which is initially cleared) and the
.gint.data.sh3 and .gint.bss.sh3 sections that are dropped on the
SH4-only fx-CG 50 are also still used.
2020-07-10 16:36:05 +02:00
Lephe 0aceb6f93e
kernel: compact VBR even more on SH3
This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in
the gap between the exception and TLB miss handlers.

This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large
block numbers can be used to jump over the TLB miss handler and the
interrupt handler entry points.
2020-07-10 13:07:12 +02:00
Lephe 2b1f408cb4
kernel: compact VBR scheme on SH3
I have recenty discovered that the so-called "rram" section used by gint
to store its VBR space and a couple memory structures gets overwritten
when returning to the main menu. It is thus necessary to get rid of it
and store that data somewhere else.

My current lead is to have it at the start of the static RAM by querying
its address in the TLB. However, the static RAM is very small on SH3
(8k) so the VBR must be made more compact.

This change elaborates the event code translation scheme used on SH3 to
emulate SH4 event codes. It is now used to translate the event codes to
a gint-specific VBR layout that leaves no gaps and thus reduces the size
of the VBR space. The gint_inthandler() method has to be modified for
every new SH3 interrupt to maintain this scheme.
2020-07-09 10:44:37 +02:00
Lephe 9cf2f9fe97
core tmu: improve reliability of interrupt handlers
This change includes three reliability improvements in handlers:

1. TMU handlers now actively check for the UNF flag to go low rather
   than expecting it to do so right away.
2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt
   (which is absolutely required for nested interrupts!).
3. gint_inth_callback() no longer performs transfers between user bank
   and kernel bank while in user bank, because this is when interrupts
   are enabled and thus likely to corrupt the kernel bank; rather, it
   now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
Lephe 2fd4238d31
core: finalize TLB management in timer callbacks (STABLE)
This change enables interrupts within timer callbacks, making it
possible to load pages to MMU while handling a timer underflow. The call
to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid
jumping to ILRAM for a short call on SH4.

The TMU and ETMU handlers have been changed to callback through a new
function gint_inth_callback() that saves the user bank and a few
registers, then invokes the callback with interrupts enabled and in user
bank; until now, callbacks were invoked with interrupts disabled and in
kernel bank. Note that IMASK is still set so a callback can only be
interrupted by a high-priority interrupt.

A timer_wait() function has also been added to simplify tests that
involve timers. Finally, the priority level of the TMU0 underflow
interrupt has been set to 13 (as per the comments) instead of 7.

This version is the first stable version that handles TLB misses
transparently for large add-ins. It is suitable for every gint
application.
2020-06-17 11:43:26 +02:00
Lephe 2cdf925f94
interrupts: save caller-saved registers in main handler
This is an obvious requirement for the interrupt routine, which was
forgotten and only surfaced when I used a timer callback started with
multiplications in an innocent add-in. r0..r7 are saved automatically,
which leaves pr, gbr, mach et macl susceptible to corruption by the
interrupt handler.
2020-05-06 20:45:35 +02:00
lephe e1aca8d89b
exc: add exception handlers, use them in the DMA
This change introduces exception handlers that default to a fatal error
with an on-screen description of the exception and some debugging
information.

It also adds the dprint() function as a definitely-needed helper and
removes bootlog_unmapped() by using the exception handler for the fatal
error display. (Also printf() is now required in all gint add-ins; this
is sad, but space is not as much of a constraint as debugging.)

Finally, the exception handler is used to handle an interrupt which is
an exception in practice, the DMA address error. On fx-CG 50, additional
DMA-related information is displayed on the screen. This is left out on
fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
lephe 04231ea5d6 dma: add a new driver to support r61524
Also add a power interface (without driving code) and switch toolchain
because the previous sh4eb-nofpu-elf toolchain was not completely
FPU-free.
2019-03-10 15:45:34 +01:00
lephe 3f7c0a04ad way too much, including bopti/topti, timers, and more. 2019-02-21 21:00:26 +01:00
lephe 2f0e049c33 More interrupt system, exceptions, timers. 2018-08-01 20:41:36 +02:00
lephe 3b90b40dd7 Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver. 2018-04-19 13:24:26 +02:00