Commit Graph

398 Commits

Author SHA1 Message Date
Kito Cheng 6864c08b94 Change license to FreeBSD License for RISC-V
- For prevent confuse about what BSD license variant we used, 2- or
   3-clause license, we change the license to FreeBSD license to make
   it unambiguously refers to the 2-clause license.
2017-08-21 11:08:54 +02:00
Kito Cheng 363dbb9e44 Add RISC-V port for newlib
Contributor list:
    - Andrew Waterman  <andrew@sifive.com>
    - Palmer Dabbelt  <palmer@dabbelt.com>
    - Kito Cheng  <kito.cheng@gmail.com>
    - Scott Beamer  <sbeamer@eecs.berkeley.edu>
2017-08-16 18:00:58 -04:00
Richard Earnshaw d6cac3e1da [arm] Fix strcpy for unified syntax on ARMv4t thumb.
ARMv4t does not support mov between two low registers.  Now we use
unified syntax mov instructions need converting to movs.
2017-07-21 11:23:27 +01:00
Ian Tessier via newlib 4bce7ecbe1 arm: Update strcpy.c to use UAL syntax.
With this change the arm platform can now be fully compiled with Clang.

Tested by comparing the output with GCC 4.8.2, and Clang 4.0, using a
variety of arches, big/little endianness, and arm/thumb mode to verify
the generated assembly output matches between GCC vs Clang with UAL, and
also GCC with UAL vs GCC with non-UAL, for all preprocessor code blocks.

The only difference found is an extra nop at the end of the function
when compiled with GCC using armv7-a/thumb/little-endian/-O2 compared to
Clang. The nop is not emitted when compiled in big-endian mode.
2017-07-20 16:18:29 +02:00
Wilco Dijkstra c86063bdc0 Optimized memcmp
This is an optimized memcmp for AArch64.  This is a complete rewrite
using a different algorithm.  The previous version split into cases
where both inputs were aligned, the inputs were mutually aligned and
unaligned using a byte loop.  The new version combines all these cases,
while small inputs of less than 8 bytes are handled separately.

This allows the main code to be sped up using unaligned loads since
there are now at least 8 bytes to be compared.  After the first 8 bytes,
align the first input.  This ensures each iteration does at most one
unaligned access and mutually aligned inputs behave as aligned.
After the main loop, process the last 8 bytes using unaligned accesses.

This improves performance of (mutually) aligned cases by 25% and
unaligned by >500% (yes >6 times faster) on large inputs.

ChangeLog:
2017-06-28  Wilco Dijkstra  <wdijkstr@arm.com>

        * newlib/libc/machine/aarch64/memcmp.S (memcmp):
        Rewrite of optimized memcmp.

GLIBC benchtests/bench-memcmp.c performance comparison for Cortex-A53:

Length    1, alignment  1/ 1:		153%
Length    1, alignment  1/ 1:		119%
Length    1, alignment  1/ 1:		154%
Length    2, alignment  2/ 2:		121%
Length    2, alignment  2/ 2:		140%
Length    2, alignment  2/ 2:		121%
Length    3, alignment  3/ 3:		105%
Length    3, alignment  3/ 3:		105%
Length    3, alignment  3/ 3:		105%
Length    4, alignment  4/ 4:		155%
Length    4, alignment  4/ 4:		154%
Length    4, alignment  4/ 4:		161%
Length    5, alignment  5/ 5:		173%
Length    5, alignment  5/ 5:		173%
Length    5, alignment  5/ 5:		173%
Length    6, alignment  6/ 6:		145%
Length    6, alignment  6/ 6:		145%
Length    6, alignment  6/ 6:		145%
Length    7, alignment  7/ 7:		125%
Length    7, alignment  7/ 7:		125%
Length    7, alignment  7/ 7:		125%
Length    8, alignment  8/ 8:		111%
Length    8, alignment  8/ 8:		130%
Length    8, alignment  8/ 8:		124%
Length    9, alignment  9/ 9:		160%
Length    9, alignment  9/ 9:		160%
Length    9, alignment  9/ 9:		150%
Length   10, alignment 10/10:		170%
Length   10, alignment 10/10:		137%
Length   10, alignment 10/10:		150%
Length   11, alignment 11/11:		160%
Length   11, alignment 11/11:		160%
Length   11, alignment 11/11:		160%
Length   12, alignment 12/12:		146%
Length   12, alignment 12/12:		168%
Length   12, alignment 12/12:		156%
Length   13, alignment 13/13:		167%
Length   13, alignment 13/13:		167%
Length   13, alignment 13/13:		173%
Length   14, alignment 14/14:		167%
Length   14, alignment 14/14:		168%
Length   14, alignment 14/14:		168%
Length   15, alignment 15/15:		168%
Length   15, alignment 15/15:		173%
Length   15, alignment 15/15:		173%
Length    1, alignment  0/ 0:		134%
Length    1, alignment  0/ 0:		127%
Length    1, alignment  0/ 0:		119%
Length    2, alignment  0/ 0:		94%
Length    2, alignment  0/ 0:		94%
Length    2, alignment  0/ 0:		106%
Length    3, alignment  0/ 0:		82%
Length    3, alignment  0/ 0:		87%
Length    3, alignment  0/ 0:		82%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		122%
Length    5, alignment  0/ 0:		127%
Length    5, alignment  0/ 0:		119%
Length    5, alignment  0/ 0:		127%
Length    6, alignment  0/ 0:		103%
Length    6, alignment  0/ 0:		100%
Length    6, alignment  0/ 0:		100%
Length    7, alignment  0/ 0:		82%
Length    7, alignment  0/ 0:		91%
Length    7, alignment  0/ 0:		87%
Length    8, alignment  0/ 0:		111%
Length    8, alignment  0/ 0:		124%
Length    8, alignment  0/ 0:		124%
Length    9, alignment  0/ 0:		136%
Length    9, alignment  0/ 0:		136%
Length    9, alignment  0/ 0:		136%
Length   10, alignment  0/ 0:		136%
Length   10, alignment  0/ 0:		135%
Length   10, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		135%
Length   12, alignment  0/ 0:		136%
Length   12, alignment  0/ 0:		136%
Length   12, alignment  0/ 0:		136%
Length   13, alignment  0/ 0:		135%
Length   13, alignment  0/ 0:		136%
Length   13, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length   32, alignment  0/ 0:		127%
Length   32, alignment  7/ 2:		395%
Length   32, alignment  0/ 0:		127%
Length   32, alignment  0/ 0:		127%
Length    8, alignment  0/ 0:		111%
Length    8, alignment  0/ 0:		124%
Length    8, alignment  0/ 0:		124%
Length   64, alignment  0/ 0:		128%
Length   64, alignment  6/ 4:		475%
Length   64, alignment  0/ 0:		131%
Length   64, alignment  0/ 0:		134%
Length   16, alignment  0/ 0:		128%
Length   16, alignment  0/ 0:		119%
Length   16, alignment  0/ 0:		128%
Length  128, alignment  0/ 0:		129%
Length  128, alignment  5/ 6:		475%
Length  128, alignment  0/ 0:		130%
Length  128, alignment  0/ 0:		129%
Length   32, alignment  0/ 0:		126%
Length   32, alignment  0/ 0:		126%
Length   32, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		127%
Length  256, alignment  4/ 8:		545%
Length  256, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		128%
Length   64, alignment  0/ 0:		171%
Length   64, alignment  0/ 0:		171%
Length   64, alignment  0/ 0:		174%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  3/10:		585%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  0/ 0:		127%
Length  128, alignment  0/ 0:		129%
Length  128, alignment  0/ 0:		128%
Length  128, alignment  0/ 0:		129%
Length 1024, alignment  0/ 0:		125%
Length 1024, alignment  2/12:		611%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		128%
Length  256, alignment  0/ 0:		127%
Length  256, alignment  0/ 0:		128%
Length 2048, alignment  0/ 0:		125%
Length 2048, alignment  1/14:		625%
Length 2048, alignment  0/ 0:		125%
Length 2048, alignment  0/ 0:		125%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  0/ 0:		127%
Length  512, alignment  0/ 0:		127%
Length 4096, alignment  0/ 0:		125%
Length 4096, alignment  0/16:		125%
Length 4096, alignment  0/ 0:		125%
Length 4096, alignment  0/ 0:		125%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length 8192, alignment  0/ 0:		125%
Length 8192, alignment 63/18:		636%
Length 8192, alignment  0/ 0:		125%
Length 8192, alignment  0/ 0:		125%
Length   16, alignment  1/ 2:		317%
Length   16, alignment  1/ 2:		317%
Length   16, alignment  1/ 2:		317%
Length   32, alignment  2/ 4:		395%
Length   32, alignment  2/ 4:		395%
Length   32, alignment  2/ 4:		398%
Length   64, alignment  3/ 6:		475%
Length   64, alignment  3/ 6:		475%
Length   64, alignment  3/ 6:		477%
Length  128, alignment  4/ 8:		479%
Length  128, alignment  4/ 8:		479%
Length  128, alignment  4/ 8:		479%
Length  256, alignment  5/10:		543%
Length  256, alignment  5/10:		539%
Length  256, alignment  5/10:		543%
Length  512, alignment  6/12:		585%
Length  512, alignment  6/12:		585%
Length  512, alignment  6/12:		585%
Length 1024, alignment  7/14:		611%
Length 1024, alignment  7/14:		611%
Length 1024, alignment  7/14:		611%
2017-06-29 20:36:35 +02:00
Sebastian Pop 9938a64ca9 aarch64: optimize the unaligned case of memcmp
This brings to newlib a performance improvement that we developed in Bionic
libc.  That change has been submitted for review to Bionic libc:
https://android-review.googlesource.com/418279

A similar patch has been submitted for review in glibc:
https://sourceware.org/ml/libc-alpha/2017-06/msg01143.html

Patch written by Vikas Sinha and Sebastian Pop.

The performance was measured on the bionic-benchmarks on a hikey (aarch64 8xA53)
board. There was no performance change to the existing benchmark
and a performance improvement on the new benchmark for memcmp
on the unaligned side. The new benchmark has been submitted for
review at https://android-review.googlesource.com/414860

The overall performance improves by 18% for the small data set 8
and the performance improves by 450% for the large data set 64k.

The base is with the libc from /system/lib64. The bionic libc
with this patch is in /data.

hikey:/data # export LD_LIBRARY_PATH=/system/lib64
hikey:/data # ./bionic-benchmarks --benchmark_filter='BM_string_memcmp*'
Run on (8 X 2.4 MHz CPU s)
Benchmark                                Time           CPU Iterations
----------------------------------------------------------------------
BM_string_memcmp/8                      30 ns         30 ns   22955680    251.07MB/s
BM_string_memcmp/64                     57 ns         57 ns   12349184   1076.99MB/s
BM_string_memcmp/512                   305 ns        305 ns    2297163   1.56496GB/s
BM_string_memcmp/1024                  571 ns        571 ns    1225211   1.66912GB/s
BM_string_memcmp/8k                   4307 ns       4306 ns     162562   1.77177GB/s
BM_string_memcmp/16k                  8676 ns       8675 ns      80676   1.75887GB/s
BM_string_memcmp/32k                 19233 ns      19230 ns      36394   1.58695GB/s
BM_string_memcmp/64k                 36986 ns      36984 ns      18952   1.65029GB/s
BM_string_memcmp_aligned/8             199 ns        199 ns    3519166   38.3336MB/s
BM_string_memcmp_aligned/64            386 ns        386 ns    1810734   158.073MB/s
BM_string_memcmp_aligned/512          1735 ns       1734 ns     403981   281.525MB/s
BM_string_memcmp_aligned/1024         3200 ns       3200 ns     218838   305.151MB/s
BM_string_memcmp_aligned/8k          25084 ns      25080 ns      28180   311.507MB/s
BM_string_memcmp_aligned/16k         51730 ns      51729 ns      13521   302.057MB/s
BM_string_memcmp_aligned/32k        103228 ns     103228 ns       6782   302.727MB/s
BM_string_memcmp_aligned/64k        207117 ns     207087 ns       3450   301.806MB/s
BM_string_memcmp_unaligned/8           339 ns        339 ns    2070998   22.5302MB/s
BM_string_memcmp_unaligned/64         1392 ns       1392 ns     502796   43.8454MB/s
BM_string_memcmp_unaligned/512        9194 ns       9194 ns      76133   53.1104MB/s
BM_string_memcmp_unaligned/1024      18325 ns      18323 ns      38206   53.2963MB/s
BM_string_memcmp_unaligned/8k       148579 ns     148574 ns       4713   52.5831MB/s
BM_string_memcmp_unaligned/16k      298169 ns     298120 ns       2344   52.4118MB/s
BM_string_memcmp_unaligned/32k      598813 ns     598797 ns       1085    52.188MB/s
BM_string_memcmp_unaligned/64k     1196079 ns    1196083 ns        540   52.2539MB/s

hikey:/data # export LD_LIBRARY_PATH=/data
hikey:/data # ./bionic-benchmarks --benchmark_filter='BM_string_memcmp*'
Run on (8 X 2.4 MHz CPU s)
Benchmark                                Time           CPU Iterations
----------------------------------------------------------------------
BM_string_memcmp/8                      30 ns         30 ns   23209918   252.802MB/s
BM_string_memcmp/64                     57 ns         57 ns   12348447   1076.95MB/s
BM_string_memcmp/512                   305 ns        305 ns    2296878   1.56471GB/s
BM_string_memcmp/1024                  572 ns        571 ns    1224426    1.6689GB/s
BM_string_memcmp/8k                   4309 ns       4308 ns     162491   1.77109GB/s
BM_string_memcmp/16k                  9348 ns       9345 ns      74894   1.63285GB/s
BM_string_memcmp/32k                 18329 ns      18322 ns      38249    1.6656GB/s
BM_string_memcmp/64k                 36992 ns      36981 ns      18952   1.65045GB/s
BM_string_memcmp_aligned/8             199 ns        199 ns    3513925   38.3162MB/s
BM_string_memcmp_aligned/64            386 ns        386 ns    1814038   158.192MB/s
BM_string_memcmp_aligned/512          1735 ns       1735 ns     402279   281.502MB/s
BM_string_memcmp_aligned/1024         3204 ns       3202 ns     218761   304.941MB/s
BM_string_memcmp_aligned/8k          25577 ns      25569 ns      27406   305.548MB/s
BM_string_memcmp_aligned/16k         52143 ns      52123 ns      13522   299.769MB/s
BM_string_memcmp_aligned/32k        105169 ns     105127 ns       6637    297.26MB/s
BM_string_memcmp_aligned/64k        206508 ns     206383 ns       3417   302.835MB/s
BM_string_memcmp_unaligned/8           282 ns        282 ns    2482953    27.062MB/s
BM_string_memcmp_unaligned/64          542 ns        541 ns    1298317    112.77MB/s
BM_string_memcmp_unaligned/512        2152 ns       2152 ns     325267   226.915MB/s
BM_string_memcmp_unaligned/1024       4025 ns       4025 ns     173904   242.622MB/s
BM_string_memcmp_unaligned/8k        32276 ns      32271 ns      21818    242.09MB/s
BM_string_memcmp_unaligned/16k       65970 ns      65970 ns      10554   236.851MB/s
BM_string_memcmp_unaligned/32k      131241 ns     131242 ns       5129    238.11MB/s
BM_string_memcmp_unaligned/64k      266159 ns     266160 ns       2661   234.821MB/s
2017-06-26 10:22:40 +02:00
Prakhar Bahuguna 21ff2cf930 Fix minor issues in memchr NEON implementation 2017-06-07 12:16:15 +02:00
Sebastian Huber 2693c1db69 Move ARM access.c from machine to sys
The implementation of the POSIX access() function is nothing machine
specific like memcpy(), etc.  Move it back to the system domain.  This
avoids problems due to the include search order of the Newlib/GCC build
which picks up machine includes before system includes.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2017-05-25 12:34:53 -04:00
Prakhar Bahuguna c47c9bdc1b Optimise memchr for NEON-enabled processors 2017-04-06 18:19:20 +02:00
Catherine Moore 571c69656a Use .syntax unified instead of .syntax divided. 2017-03-30 17:18:12 +02:00
Kyrill Tkachov 52a6da816f arm: Fix addressing in optpld macro
In patch b219285f87 you have a syntax
error in the PLD instruction.  The syntax for the pld argument should be
in square brackets as it's a memory address like so: pld [r1].  With
your patch the newlib build fails for armv7-a targets.  This patch fixes
the build failures.

Tested by making sure the newlib build completes successfully.

2016-01-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * libc/machine/arm/strcpy.c (strcpy): Fix PLD assembly syntax.
    * libc/machine/arm/strlen-stub.c (strlen): Likewise.
2017-01-26 16:29:36 +01:00
Pat Pannuto 3ebc26958e arm: Remove RETURN macro
LTO can re-order top-level assembly blocks, which can cause this
macro definition to appear after its use (or not at all), causing
compilation failures. On modern toolchains (armv4t+), assembly
should write `bx lr` in all cases, and linkers will transparently
convert them to `mov pc, lr`, allowing us to simply remove the
macro.
  (source: https://groups.google.com/forum/#!topic/comp.sys.arm/3l7fVGX-Wug
   and verified empirically)

For the armv4.S file, preserve this macro to maximize backwards
compatibility.
2017-01-25 13:32:09 +01:00
Pat Pannuto b219285f87 arm: Remove optpld macro
LTO can re-order top-level assembly blocks, which can cause this
macro definition to appear after its use (or not at all), causing
compilation failures. As the macro has very few uses, simply removing
it by inlining is a simple fix.

n.b. one of the macro invocations in strlen-stub.c was already
guarded by the relevant #define, so it is simply converted directly
to a pld
2017-01-25 13:32:09 +01:00
Pat Pannuto e7332409cc Remove unneeded references to arm_asm.h
This should result in no functional changes, it simply removes references
to arm_asm.h that did not use anything from that file.
2017-01-25 13:32:09 +01:00
Jeff Johnston 61f181d6b8 Bump release to 2.5.0 for yearly snapshot. 2016-12-22 21:33:54 -05:00
Julian Brown bc4f996f56 Big-endian fix for memcpy-armv7m.S
In the case of memcpy-armv7m.S being built for a big-endian multilib
(including armv7 without a specific profile), realignment code made
assumptions about the byte ordering being little-endian.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2016-12-12 11:23:45 +01:00
Anton Kolesov 668033eb9f arc: Fix strcmp for big endian without barrel shifter
strcmp.S contained invalid guard for code that used barrel-shifter optional
instruction - it was checking for !ARC601 instead of whether barrel shifter
is present. While it is true that ARC601 doesn't have barrel shifter, so
does some other ARC EM configurations.

2016-07-21  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* libc/machine/arc/strcmp.S: Fix big endian without barrel shifter.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2016-08-11 10:59:54 +02:00
Claudiu Zissulescu 7b1080d9aa arc: Use prefetch instead of prealloc.
Prealloc instruction may not be present in all HS variants. Hence, use
prefetch instead of prealloc.

newlib/
2016-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* libc/machine/arc/memset-archs.S: Use prefetch.
2016-08-11 10:59:53 +02:00
Claudiu Zissulescu 67c5af5b85 arc: Use unaligned loads/stores for memcopy.
newlib/
2016-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* libc/machine/arc/memcpy-archs.S: Add and enable memcpy using
	unaligned loads/stores.
2016-08-11 10:59:53 +02:00
Jon Turney d7e47a557e Regenerate newlib Makefiles 2016-07-04 17:13:55 +01:00
Jon Turney 0b4cbd2fb8 Make newlib manpages (v3)
Add makedocbook, a tool to process makedoc markup and output DocBook XML
refentries.

Process all the source files which are processed with makedoc with
makedocbook as well

Add chapter-texi2docbook, a tool to automatically generate DocBook XML
chapter files from the chapter .texi files.  For generating man pages all we
care about is the content of the refentries, so all this needs to do is
convert the @include of the makedoc generated .def files to xi:include of
the makedocbook generated .xml files.

Add skeleton Docbook XML book files, lib[cm].in.xml which include these
generated chapters, which in turn include the generated files containing
refentries, which is processed with xsltproc to generate the lib[cm].xml

Add new make targets to generate and install man pages from lib[cm].xml
2016-07-04 14:17:10 +01:00
Jon Turney f145c2e261 Revert "Make newlib manpages via DocBook XML (v3)"
This reverts commit 041ea41068.
2016-06-25 17:07:43 +01:00
Jon Turney 041ea41068 Make newlib manpages via DocBook XML (v3)
Add makedocbook, a tool to process makedoc markup and output DocBook XML
refentries.

Process all the source files which are processed with makedoc with
makedocbook as well

Add chapter-texi2docbook, a tool to automatically generate DocBook XML
chapter files from the chapter .texi files.  For generating man pages all we
care about is the content of the refentries, so all this needs to do is
convert the @include of the makedoc generated .def files to xi:include of
the makedocbook generated .xml files.

Add skeleton Docbook XML book files, lib[cm].in.xml which include these
generated chapters, which in turn include the generated files containing
refentries, which is processed with xsltproc to generate the lib[cm].xml

Add new make targets to generate and install man pages from lib[cm].xml
2016-06-25 17:04:15 +01:00
Wilco Dijkstra e7b1ee2ea6 Add rawmemchr
Marcus Shawcroft wrote:
> This patch appears to have been munged by the mail system, can you
> repost as an attachment please.

Sure, I've attached the patch.

Wilco

Add a simple rawmemchr implementation. Use strlen for rawmemchr(s, '\0') as it is the
fastest way to search for '\0', and use memchr with an infinite size for other cases.
This is 3x faster for large sizes.

ChangeLog:
2016-04-22  Wilco Dijkstra  <wdijkstr@arm.com>

        * newlib/libc/machine/aarch64/Makefile.in: Add rawmemchr.S and
        rawmemchr-stub.c.
        * newlib/libc/machine/aarch64/Makefile.am: Likewise.
        * newlib/libc/machine/aarch64/rawmemchr.S (rawmemchr): Add rawmemchr.
        * newlib/libc/machine/aarch64/rawmemchr-stub.c (rawmemchr): Likewise.
2016-05-20 10:47:02 +02:00
Jeff Johnston 5c02bcc086 Fix strlen using Thumb-2 with -Os -marm
2016-04-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

        * libc/machine/arm/strlen-stub.c: Check capabilities of architecture
        to decide which Thumb implementation to use and fall back to C
        implementation for architecture not supporting Thumb mode.
        * libc/machine/arm/strlen.S: Likewise.
2016-05-11 17:18:48 -04:00
Sebastian Huber 76a2110b47 BSD compatibility for <machine/endian.h>
Introduce <machine/_endian.h> to let target based customization of
<machine/endian.h> via

 * _LITTLE_ENDIAN,
 * _BIG_ENDIAN,
 * _PDP_ENDIAN, and
 * _BYTE_ORDER.

defines.  Add definitions expected by FreeBSD to
<machine/endian.h> like

 * _QUAD_HIGHWORD,
 * _QUAD_LOWWORD,
 * __bswap16(),
 * __bswap32(),
 * __bswap64(),
 * __htonl(),
 * __htons(),
 * __ntohl(), and
 * __ntohs().

Also, if __BSD_VISIBLE

 * LITTLE_ENDIAN,
 * BIG_ENDIAN,
 * PDP_ENDIAN, and
 * BYTE_ORDER.

Targets that define __machine_host_to_from_network_defined in
<machine/_endian.h> must provide their own implementation of

 * __htonl(),
 * __htons(),
 * __ntohl(), and
 * __ntohs(),

otherwise a default implementation is provided by <machine/endian.h>.
In case of GCC defines to builtins are used.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2016-04-19 16:36:51 +02:00
Sebastian Huber 8a5af1a184 Use __machine_*_t_defined for internal types
Newlib defines defaults for internal types via <sys/_types.h> and uses
<machine/_types.h> to let targets define their own type if necessary.

Previously for example

	#ifndef __dev_t_defined
	typedef short __dev_t;
	#endif

However, the __*_t_defined pattern conflicts with the glibc type guard
pattern for user types, e.g. dev_t in this example.  Introduce a
__machine_*_t_defined pattern for internal types (defined by
<machine/_types.h>, used by <sys/_types.h>).  For example

	#ifndef __machine_dev_t_defined
	typedef short __dev_t;
	#endif

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2016-04-15 14:51:39 +02:00
Igor Venevtsev 5d3ad3b123 Add Intel MCU target
Intel MCU System V ABI are incompartible with i386 System V ABI:
    o Minimum instruction set is Intel Pentium ISA minus x87 instructions
    o No x87 or vector registers
    o First three args are passed in %eax, %edx and %ecx
    o Full specification available here:
      https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf

newlib/
    * configure.host: Add new ix86-*-elfiamcu target

newlib/libc/include/
    * setjmp.h: Change _JBLEN for Intel MCU target

newlib/libc/machine/i386/
    * memchr.S:  (memchr)  Target-specific size-optimized version
    * memcmp.S:  (memcmp)  Likewise
    * memcpy.S:  (memcpy)  Likewise
    * memmove.S: (memmove) Likewise
    * memset.S:  (memset)  Likewise
    * setjmp.S:  (setjmp)  Likewise
    * strchr.S:  (strchr)  Likewise
    * strlen.S:  (strlen)  Likewise

newlib/libc/stdlib/
    * srtold.c:  (__flt_rounds) Disable for Intel MCU
2016-04-04 16:32:07 +02:00
Jeff Johnston fbc4a0827b Bump up newlib version to 2.4.0 due to feature test refactoring 2016-03-29 17:33:42 -04:00
Joel Sherrill ecf453f963 Add simple versions of random() and srandom()
Prototypes also added for initstate() and setstate() but they
were not implemented in the shared newlib code.

	* newlib/libc/include/cygwin/stdlib.h: Prototypes added.
	* winsup/cygwin/include/cygwin/stdlib.h: Prototypes removed.
	* newlib/libc/stdlib/random.c: New file.
	* newlib/libc/machine/epiphany/machine/stdlib.h: Removed
	* newlib/libc/stdlib/Makefile.am: Added random.c.
	* newlib/libc/stdlib/stdlib.tex: Added random.def.
	* newlib/libc/stdlib/Makefile.in: Regenerated.
2016-03-28 22:39:50 -05:00
Joel Sherrill 13707ae933 epiphany/machine/stdlib.h: Disable epiphany unique random wrappers for RTEMS 2016-03-22 09:47:00 -05:00
Corinna Vinschen b9217601f8 Enable HW interrupt setup on x86/x86_64 systems by default
* configure.host: Define _I386MACH_DISABLE_HW_INTERRUPTS on rdos.
	Remove setting _I386MACH_ALLOW_HW_INTERRUPTS anywhere else.
	* libc/machine/i386/i386mach.h: Replace test for
	_I386MACH_ALLOW_HW_INTERRUPTS with test for
	!_I386MACH_DISABLE_HW_INTERRUPTS.
	* libc/machine/x86_64/x86_64mach.h: Ditto.
	* libc/sys/linux/machine/i386/i386mach.h: Ditto.
	* libm/machine/i386/i386mach.h: Ditto.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2016-02-26 18:52:46 +01:00
Steve Ellcey 4792146a0f Fix memcpy bug that reads past end of buffer.
* libc/machine/mips/memcpy.S (memcpy): Fix read past end of
	input.
2016-01-28 14:08:35 -08:00
Thomas Preud'homme 69f4c40291 Make macro checks ARMv8-M baseline proof
libgloss:

        * arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
        newlib is present.
        * arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macros __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
        !__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
        PREFER_THUMB rather than THUMB_V7_V6M.  Rename other occurences of
        THUMB_V7M_V6M to THUMB_VXM.
        * arm/linux-crt0.c: Likewise.
        * arm/redboot-crt0.S: Likewise.
        * arm/swi.h: Likewise.
        * arm/trap.S: Likewise.

newlib:

        * libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
        and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
        __ARM_ARCH and __ARM_ARCH_PROFILE.
        * libc/machine/arm/memcpy.S: Likewise.
        * libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
        include acle-compat.h.
        * libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
        target and include acle-compat.h.
        * libc/sys/arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macro __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
        rename THUMB_V7M_V6M into THUMB_VXM.
        * libc/sys/arm/swi.h: Likewise.
2016-01-28 11:26:37 +01:00
Jeff Johnston ad7b3cde9c Regenerate files for newlib 2.3.0. 2015-12-21 21:32:11 -05:00
Anton Kolesov 06537f05d4 ARC: Use new definitions for optional ARC CPU features
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:

    * __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
      -mbarrel-shifter
    * __ARC_LL64__ instead of __LL64__ for -mll64
    * __ARCEM__ instead of __EM__ for -mcpu=arcem
    * __ARCHS__ instead of __HS__ for -mcpu=archs
    * etc (not used in newlib)

This patch updates assembly routines for ARC to use new definitions instead
of a deprecated ones. To ensure compatibility with older compiler new
definitions are also defined in asm.h if needed, based on deprecated
preprocessor definitions.

*** newlib/ChangeLog ***
2015-12-15  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* libc/machine/arc/asm.h: Define new GCC definition for old compiler.
	* libc/machine/arc/memcmp-bs-norm.S: Use new GCC defines to detect
	  processor features.
	* libc/machine/arc/memcmp.S: Likewise.
	* libc/machine/arc/memcpy-archs.S: Likewise.
	* libc/machine/arc/memcpy-bs.S: Likewise.
	* libc/machine/arc/memcpy.S: Likewise.
	* libc/machine/arc/memset-archs.S: Likewise.
	* libc/machine/arc/memset-bs.S: Likewise.
	* libc/machine/arc/memset.S: Likewise.
	* libc/machine/arc/setjmp.S: Likewise.
	* libc/machine/arc/strchr-bs-norm.S: Likewise.
	* libc/machine/arc/strchr-bs.S: Likewise.
	* libc/machine/arc/strchr.S: Likewise.
	* libc/machine/arc/strcmp-archs.S: Likewise.
	* libc/machine/arc/strcmp.S: Likewise.
	* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
	* libc/machine/arc/strcpy-bs.S: Likewise.
	* libc/machine/arc/strcpy.S: Likewise.
	* libc/machine/arc/strlen-bs-norm.S: Likewise.
	* libc/machine/arc/strlen-bs.S: Likewise.
	* libc/machine/arc/strlen.S: Likewise.
	* libc/machine/arc/strncpy-bs.S: Likewise.
	* libc/machine/arc/strncpy.S: Likewise.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2015-12-17 22:48:16 +01:00
Marcus Shawcroft 8e62ab4ccc [ARM] Adjust strcmp-armv7.S selection logic.
Reformulate the strcmp-armv7.S selection logic around the architecture
features required by the implementation code rather (some) version of
the architecture that expose those features.
2015-11-23 15:22:26 +00:00
Marcus Shawcroft dc38827570 [ARM] Factor out the thumb2 -Os implementation.
The patch moves the inline ASM thumb2 -Os implementation out into its
own .S file.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-23 15:21:47 +00:00
Corinna Vinschen fbace81684 Import correctly working strtold from David M. Gay.
* libc/stdlib/Makefile.am (GENERAL_SOURCES): Add strtodg.c and
	strtorx.c.
	* libc/stdlib/Makefile.in: Regenerate.
	* libc/stdlib/strtodg.c: New file implementing generic string to long
	double conversion.
	* libc/stdlib/strtorx.c: New file, implementing IEEE format string to
	long double conversion.
	* libc/stdlib/mprec.h (_strtodg_r): Declare.
	(_strtorx_r): Declare.
	* libc/stdlib/gdtoa.h (__UShort): Define.
	* libc/stdlib/strtold.c (__flt_rounds): Define for i386 and x86_64
	target.
	(FLT_ROUNDS): Define, as 0 on platforms missing a __flt_rounds
	function.
	(_strtold_r): Converted from strtold.  Call _strtorx_r on targets
	supporting distinct long doubles.
	(strtold): Just call _strtold_r.
	* libc/include/stdlib.h (_strtold_r): Declare.
	* libc/stdlib/ldtoa.c (_strtold): Comment out.  Explain why.
	* libc/stdio/vfscanf.c (__SVFSCANF_R): Call _strtold_r instead of
	_strtold.
	* libc/machine/powerpc/vfscanf.c (__svfscanf_r): Ditto.

	* common.din (strtold): Drop redirection to _strtold.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2015-11-20 18:14:58 +01:00
Marcus Shawcroft 9959058932 [ARM] Factor out the thumb1 -Os implementation.
The patch moves the inline ASM thumb1 -O2 implementation out into its
own .S file.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:28 +00:00
Marcus Shawcroft bcd5e8e3f9 [ARM] Adding strlen.S
The patch adds strlen.S to contain the complementary preprocessor
logic to strlen-stub.c intended to provide #inclusion of alternative
.S implementations.

Initially we just include the existing strlen-armv7.S implementation.

We rewrite _ISA_ARMV7 in both strlen.S and strlen-stub.c to use the
underlying existing underlying defintion from arm_asm.h in order to
avoide including that file, this is in effect the first step towards a
move to ACLE predefines only.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:28 +00:00
Marcus Shawcroft 42de6f5085 [ARM] Rename strlen to strlen-stub.c
In order to maintain consistency both within machine/arm and between
machine/arm and machine/aarch64, rename the 'c' stub to -stub.c.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
       Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:23 +00:00
Marcus Shawcroft 2c8e31d654 [ARM] Reorganize strlen selection.
Remove automake and autoconf selection of strchr implementation in
favour of conditional compilation in strlen.c.
2015-11-13 11:52:01 +00:00
Marcus Shawcroft 52f5864096 [ARM] Refactor strlen.c #if nesting.
This patch flattens the condition code selection used in strlen in an
attempt to make the guarding condition for each alternative
implementation clearer and to structure the logic in a manner that
makes it easier to maintain complementary logic between the
alternative 'C' and assembler implementations.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

  Architectures:
    armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
    armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
    armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

  ISAs:
    thumb arm

  Optimization Levels:
    Os O2

  Excluding:
    armv6s-m -mthumb
    armv6-m -mthumb

    armv6zk -mthumb
    armv6z -mthumb
    armv6k -mthumb
    armv6j -mthumb
2015-11-13 11:51:31 +00:00
Anton Kolesov c0a99f0293 Add support for ARC to newlib
newlib/ChangeLog:
2015-11-12  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* configure.host: Add ARC support.
	* libc/include/machine/setjmp.h: Likewise.
	* libc/machine/configure: Likewise.
	* libc/machine/configure.in: Likewise.
	* libc/machine/arc/Makefile.am: Likewise.
	* libc/machine/arc/Makefile.in: Likewise.
	* libc/machine/arc/aclocal.m4: Likewise.
	* libc/machine/arc/asm.h: Likewise.
	* libc/machine/arc/configure: Likewise.
	* libc/machine/arc/configure.in: Likewise.
	* libc/machine/arc/memcmp-bs-norm.S: Likewise.
	* libc/machine/arc/memcmp-stub.c: Likewise.
	* libc/machine/arc/memcmp.S: Likewise.
	* libc/machine/arc/memcpy-archs.S: Likewise.
	* libc/machine/arc/memcpy-bs.S: Likewise.
	* libc/machine/arc/memcpy-stub.c: Likewise.
	* libc/machine/arc/memcpy.S: Likewise.
	* libc/machine/arc/memset-archs.S: Likewise.
	* libc/machine/arc/memset-bs.S: Likewise.
	* libc/machine/arc/memset-stub.c: Likewise.
	* libc/machine/arc/memset.S: Likewise.
	* libc/machine/arc/setjmp.S: Likewise.
	* libc/machine/arc/strchr-bs-norm.S: Likewise.
	* libc/machine/arc/strchr-bs.S: Likewise.
	* libc/machine/arc/strchr-stub.c: Likewise.
	* libc/machine/arc/strchr.S: Likewise.
	* libc/machine/arc/strcmp-archs.S: Likewise.
	* libc/machine/arc/strcmp-stub.c: Likewise.
	* libc/machine/arc/strcmp.S: Likewise.
	* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
	* libc/machine/arc/strcpy-bs.S: Likewise.
	* libc/machine/arc/strcpy-stub.c: Likewise.
	* libc/machine/arc/strcpy.S: Likewise.
	* libc/machine/arc/strlen-bs-norm.S: Likewise.
	* libc/machine/arc/strlen-bs.S: Likewise.
	* libc/machine/arc/strlen-stub.c: Likewise.
	* libc/machine/arc/strlen.S: Likewise.
	* libc/machine/arc/strncpy-bs.S: Likewise.
	* libc/machine/arc/strncpy-stub.c: Likewise.
	* libc/machine/arc/strncpy.S: Likewise.
2015-11-12 14:14:17 +01:00
Wilco Dijkstra 3c8636acf6 AArch64: Tune memcpy
* newlib/libc/machine/aarch64/memcpy.S (memcpy):
 	Further tuning for performance.
2015-11-12 13:38:39 +01:00
Joseph Myers e6459123e4 Avoid .eh_frame in ARM newlib.
ARM newlib has various strcmp implementations that use .cfi_*
directives to generate unwind information.

The effect of this is that the generated objects contain .eh_frame
sections.  However, ARM uses its own unwind info format, not
.eh_frame, which is generated by ARM-specific directives, not .cfi_*.
The .eh_frame sections are useless, but also not removed by strip and
may be loaded into memory at runtime.

This patch fixes this by using .cfi_sections .debug_frame (as in
glibc) so that the directives generate .debug_frame instead.
.debug_frame is useful for the debugger, can be removed by strip, and
is not loaded into memory at runtime.

	* libc/machine/arm/strcmp-arm-tiny.S: Use .cfi_sections
	.debug_frame.
	* libc/machine/arm/strcmp-armv4.S: Likewise.
	* libc/machine/arm/strcmp-armv4t.S: Likewise.
	* libc/machine/arm/strcmp-armv6.S: Likewise.
	* libc/machine/arm/strcmp-armv6m.S: Likewise.
	* libc/machine/arm/strcmp-armv7.S: Likewise.
	* libc/machine/arm/strcmp-armv7m.S: Likewise.
2015-11-12 12:09:24 +00:00
Marcus Shawcroft d18f1fc8a3 Reorganize memchr selection.
The patch cleans up the auto configury mechanism used to select
different implementations of memchr for various architecture versions.

The approach here is to remove the selection of memchr within automake
and instead use complimentary logic in memchr-stub.c and memchr.S to
choose between the gerneric memchr.c implementation or one of the
architecture specific implementations.

This patch also changes the selection criteria inline with the
previous proposal here:

https://sourceware.org/ml/newlib/2015/msg00752.html

but using the ACLE predefines.

Regressed for armv7-a armv5 armv8-a, correct selection of memcpy
implementation by manual inspection of a test program built for these
three architectures.
2015-11-06 16:11:32 +00:00
Marcus Shawcroft 72be1dead4 Reorganize memcpy selection.
This patch cleans up the auto configury mechanism used to select
different implementations of memcpy for various architecture versions.

The approach here is to remove the selection of memcpy within automake
and instead use complimentary logic in memcpy-stub.c and memcpy.S to
choose between the generic memcpy.c implemenation or one of the
architecture specific memcpy*.S implemenations.

Regressed for armv7-a armv5 armv8-a, correct selection of memcpy
implementation by manual inspection of a test program built for these
three architectures.

This revised patch flips the remaining preprocessor logic in
memcpy-stub.c to use ACLE defines as requested in the previous review
and removes the now disused HAVE_ARMV7A and HAVE_ARMV8A configure.in
support.
2015-11-06 15:40:31 +00:00
Marcus Shawcroft 0a4019eed2 [ARM] Select appropriate memcpy implementation for ARMv8-a.
The newlib configury logic that detects architecture version and
chooses an appropriate memcpy implementation does not consider
ARMv8-a.

This patch adds configury logic to detect ARMv8-a along with the
associated changes in Makefile.am and memcpy.
2015-11-03 11:04:55 +00:00