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Author SHA1 Message Date
Jiong Wang 18b47e05d3 Initializing TTBR0 to inner/outer WB 
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.

The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.

The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.

Adopted suggestion given by Richard offline to avoid using jump.

libgloss/
	* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
	cacheable WB, and no allocate on WB for arch with multiprocessor
	extension.
 2016-03-26 12:45:07 +01:00
Richard Earnshaw 639951dda7 2013-10-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 
* arm/cpu-init/rdimon-aem.S: Disable for M class cores.
	* arm/crt0.S: Don't call _rdimon_hw_init_hook for non-A class cores.
	* arm/cpu-init/Makefile.in (CPU_INIT_OBJS): Use CFLAGS.
 2013-10-14 15:15:12 +00:00
Richard Earnshaw 99be2bc4ff 2013-09-20 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 
Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
	    Greta Yorsh  <greta.yorsh@arm.com>

	* arm/Makefile.in: Add support for cpu-init directory and add
	elf-aprofile-ve.specs.
	* arm/configure.in: Likewise.
	* arm/configure: Regenerate.
	* arm/cpu-init: New directory.
	* arm/cpu-init/Makefile.in: New file.
	* arm/cpu-init/rdimon-aem.S: Likewise.
	* arm/crt0.S: Call _rdimon_init_hook
	* arm/elf-aprofile-ve.specs: New file.
 2013-09-20 14:23:41 +00:00