Commit Graph

519 Commits

Author SHA1 Message Date
Hans-Peter Nilsson cd5e7e2d82 Committed, libgloss: hook up cris-elf to the initfini-array support.
After a binutils change "a while ago" (2015-12) to default to
--enable-initfini-array, i.e. to merge .ctors and .dtors into
.init_array and .fini_array, this is needed for cdtors to run at all.

Based on what goes on in arm/ and aarch64/.  Tested for cris-elf by
running the gcc testsuite.

By the way, the configure test doesn't detect this change, so the
HAVE_INITFINI_ARRAY ifdeffery is somewhat redundant.  Still, the
change is tested to be safe with older binutils too.

libgloss/
	* cris/crt0.S, cris/lcrt0.c: Include newlib.h.
	[HAVE_INITFINI_ARRAY] (_init): Define to __libc_init_array.
	[HAVE_INITFINI_ARRAY] (_fini): Ditto __libc_fini_array.
2017-01-29 21:23:32 +01:00
Thomas Preudhomme 3ce88693f5 Fix html build with makeinfo 5.2
HTML build fails with makeinfo 5.2 with the following error:

libgloss/doc/porting.texi:73: @menu seen before first @node
libgloss/doc/porting.texi:73: perhaps your @top node should be wrapped in
@ifnottex rather than @ifinfo?

Following the advice indeed solve the issue while still allowing pdf, dvi and
info builds to work.
2016-08-19 10:32:23 +02:00
Claudiu Zissulescu 1baa8bb843 arc: Add align keyword.
libgloss/
2016-06-28  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc/crt0.S: Add align keyword.
2016-08-11 10:59:54 +02:00
Nick Clifton e6413b0a64 Add comment in the v850's crt0.S file noting that separate LMA and VMA addresses for data sections are not currently supported. 2016-05-26 12:08:47 +01:00
Anton Kolesov d1dcdb8886 arc: Have nops in _exit_halt only for ARCompact
ARCompact processors (ARC 600 and ARC 700) require three "nop"s after the
"flag 1" instruction. Later ARC processors do not have this requirement, so
it is possible to reduce size of "_exit_halt" for them.

libgloss/
2016-05-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* arc/crt0.S (_exit_halt): Insert nops only for ARCompact.
2016-05-25 12:15:51 +02:00
Anton Kolesov dd00a8e719 arc: Rework default exception handlers for ARC EM and HS
Initially crt0.S used a special function, declared as weak as a default
exception handler in interrupt vector table. To let user override individual
handlers, this function had multiple names - one for each IVT entry, which,
however, was terribly confusing for the debugger and user - because it
wasn't clear which symbol will be used as a function name in debugger.
Defining multiple separate functions - one for each handler, would resolve
the mess, but would increase code size of crt0.o.

To clean this up, this patch defines exception handlers as weak symbols as
well, but those are defined as just symbols, not functions, hence there
would be less confusion over what is what. At the same time, users still can
redefine exception handlers symbol by creating functions with respective
names.

libgloss/
2016-05-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* arc/crt0.S: Convert memory_error and friends to non-function
	  symbols.
2016-05-25 12:15:51 +02:00
Yaakov Selkowitz 6ac6e7c2bd libgloss/ft32: fix whitespace in Makefile
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2016-05-20 10:10:08 -05:00
Jeff Johnston d1d1378d13 Fix libgloss arc nsim specs file. 2016-05-11 12:45:55 -04:00
Jeff Johnston 3312579f44 Fix libgloss/arc/nano.specs file. 2016-05-06 15:56:46 -04:00
Jeff Johnston 5c968d849a Fix white-space in libgloss/arc/Makefile.in. 2016-05-05 12:02:29 -04:00
Jeff Johnston 11afe8f6b6 Fix support ARC processors without barrel-shifter
crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.

Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.

libgloss/ChangeLog

2016-04-29  Anton Kolesov  <anton.kolesov@synopsys.com>

        * arc/crt0.S: Fix support for processors without barrel-shifter.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2016-05-02 12:04:40 -04:00
Jeff Johnston cd494f7038 Update crt0.S for ARC.
This is similar to commit 06537f05d4 to the
newlib for ARC.

GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:

    * __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
      -mbarrel-shifter
    * __ARCEM__ instead of __EM__ for ARC EM cores
    * __ARCHS__ instead of __HS__ for ARC HS cores
    * etc (not used in libgloss)

This patch updates crt0.S for ARC to use new definitions instead of a
deprecated ones. To ensure compatibility with older compiler new definitions
are also defined in crt0.S if needed, based on presence of deprecated
preprocessor definitions.

libgloss/ChangeLog

2016-04-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>

        * arc/crt0.S: Use new GCC defines to detect processor features.
2016-05-02 11:58:47 -04:00
Jeff Johnston e90da68265 Add necessary infrastructure to support "nano" build of newlib.
ARC aproach to this feature is similiar to ARM's one here.

2016-04-29  Anton Kolesov  <anton.kolesov@synopsys.com>

        * arc/nano.specs: New file.
        * arc/Makefile.in: Support nano.specs.
        * arc/nsim.specs: Likewise.
2016-04-29 15:17:11 -04:00
David Hoover 5c9403eaf4 Fixed semihosting for ARM when heapinfo not provided by debugger. 2016-04-21 09:51:08 +02:00
Nick Clifton 9f664259f9 Fix typo in the name of the MSP430 attribute section of example MSP430 linker scripts. 2016-04-07 12:13:10 +01:00
Jiong Wang 18b47e05d3 Initializing TTBR0 to inner/outer WB
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.

The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.

The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.

Adopted suggestion given by Richard offline to avoid using jump.

libgloss/
	* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
	cacheable WB, and no allocate on WB for arch with multiprocessor
	extension.
2016-03-26 12:45:07 +01:00
Stefan Roesch 414c8adc8b or1k: properly restore timer
Consider the function parameter for restoring the timer
2016-03-13 12:50:23 +01:00
Stefan Roesch 81ad4e656a or1k: Fix multicore stack calculation
Change the type of the stack pointers to enable pointer calculations at byte
granularity, which is needed for the calculation of _or1k_stack_core[c] and
_or1k_exception_stack_core[c] with _or1k_stack_size and
_or1k_exception_stack_size. (util.c:53-54)
2016-03-13 12:50:05 +01:00
Nick Clifton c86b2f8e93 Remove bogus LONG(0) directives from MSP430 linker scripts. 2016-03-10 10:41:13 +00:00
Nick Clifton 9676aeef0d Seperate MSP430 cio syscalls into individual function sections.
START_FUNC: New macro.
    END_FUNC: New macro.
    exit, isatty, getpid, sc2: Use the new macros.
2016-02-09 13:44:05 +00:00
Thomas Preud'homme 69f4c40291 Make macro checks ARMv8-M baseline proof
libgloss:

        * arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
        newlib is present.
        * arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macros __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
        !__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
        PREFER_THUMB rather than THUMB_V7_V6M.  Rename other occurences of
        THUMB_V7M_V6M to THUMB_VXM.
        * arm/linux-crt0.c: Likewise.
        * arm/redboot-crt0.S: Likewise.
        * arm/swi.h: Likewise.
        * arm/trap.S: Likewise.

newlib:

        * libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
        and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
        __ARM_ARCH and __ARM_ARCH_PROFILE.
        * libc/machine/arm/memcpy.S: Likewise.
        * libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
        include acle-compat.h.
        * libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
        target and include acle-compat.h.
        * libc/sys/arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macro __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
        rename THUMB_V7M_V6M into THUMB_VXM.
        * libc/sys/arm/swi.h: Likewise.
2016-01-28 11:26:37 +01:00
Corinna Vinschen 0b42ea7960 Deprecate newlib and winsup ChangeLog files
Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2016-01-28 11:15:33 +01:00
DJ Delorie 7d5b16ab9a Build msp430-specific libnosys
The MSP430 debuggers support I/O on hardware through CIO, so
we can use a CIO-enabled library as the "nosys" library (in
addition to the libsim library, which talks to our simulator)

* configure.in: Don't build default libnosys for msp430
* configure: Regenerate.
* msp430/Makefile: Rename libcio to libnosys.
2015-12-17 16:51:41 -05:00
DJ Delorie 28d7af216e Update CIO hooks to be more flexible.
Replace the one hook we had with two to avoid underscore issues.

* msp430/cio.c: Remove, replace with...
* msp430/cio.S: New, this.
2015-12-17 16:22:52 -05:00
Kevin Buettner 725532a3b2 rl78: Don't output CR when LF is encountered in write().
The file libgloss/rl78/write.c currently contains code which outputs
\r when \n is seen.  The code will then output the \n as well.

This patch removes the bit of code that tests for \n and then outputs
\r.

I made this change to fix some failures in gdb.base/call-ar-st.exp.  In
that test, I see two carriage returns followed by a newline.  One CR is
output by the libgloss code.  The other is output by the terminal driver.

The total list of failures fixed (using the default rl78 multilib) are:

FAIL: gdb.base/call-ar-st.exp: print print_double_array(double_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_char_array(char_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: continue to tbreak2 (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak3 (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_double_array(array_d) (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak4 (timeout)
FAIL: gdb.base/call-ar-st.exp: print sum_array_print(10, *list1, *list2, *list3, *list4) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_ten_doubles(123.456, 123.456, -0.12, -1.23, 343434.8, 89.098, 3.14, -5678.12345, -0.11111111, 216.97065) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs from print_long_arg_list (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_struct_rep(*struct1, *struct2, *struct3) (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 1st dprintf (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 2nd dprintf (timeout)
FAIL: gdb.base/interrupt.exp: process is alive (the program exited)

There are no regressions.

libgloss/ChangeLog:

	* rl78/write.c (_write): Don't output CR when LF is encountered.
2015-12-16 13:38:38 -07:00
Nick Clifton 3ff65caea5 Always define __high_bsssize, do not just PROVIDE it.
* msp430/msp430xl-sim.ld (__high_bsssize): Define.
2015-12-04 10:14:10 +00:00
Nick Clifton c70d8f454a Fix initialisation of .upper.bss for the MSP430.
* msp430/msp430xl-sim.ld (__high_bsssize): Define.
2015-11-23 09:00:23 +00:00
Anton Kolesov acdfcb0a0a Add support for ARC to libgloss
ChangeLog:
2015-11-12  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* configure.in: Add ARC support to libgloss.
	* configure: Regenerate.

libgloss/ChangeLog:
2015-11-12  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* configure: Add ARC support.
	* configure.in: Likewise.
	* arc/Makefile.in: Likewise.
	* arc/aclocal.m4: Likewise.
	* arc/configure: Likewise.
	* arc/configure.in: Likewise.
	* arc/crt0.S: Likewise.
	* arc/libcfunc.c: Likewise.
	* arc/nsim-syscall.h: Likewise.
	* arc/nsim-syscalls.c: Likewise.
	* arc/nsim.specs: Likewise.
	* arc/sbrk.c: Likewise.
2015-11-12 14:11:47 +01:00
DJ Delorie 9e8f756124 * rl78/crt0.S (_start): Fixed code that clears .bss 2015-10-20 21:37:06 -04:00
Nick Clifton 3b8933900f Add support for persistent data to the MSP430 linker scripts.
* msp430/msp430-sim.ld: Add .persistent section.
	Tidy up section layout.
	Start RAM above hardware multiply registers.
	* msp430/msp430xl-sim.ld: Likewise.
2015-10-06 17:33:16 +01:00
Jeff Johnston dc09f27aaa Add support for FT32 platform. 2015-09-04 13:13:30 -04:00
Nick Clifton 9eb50ea21b oops - forgot to add PR number to ChangeLog entry. 2015-08-24 10:05:19 +01:00
Nick Clifton 23066e1b64 * msp430/crt0.S: Remove watchdog disabling code. 2015-08-20 17:19:49 +01:00
Jeff Johnston 30c6a3088b or1k: Typo fixes
Wrong paranthesis and an incorrect symbol name are fixed.

          * or1k/boards/optimsoc.S: Fix symbol name
          * or1k/crt0.S: Remove paranthesis
2015-08-07 15:02:03 -04:00
Jeff Johnston 31cf34f849 or1k: Allow exception nesting
Allow exceptions to be nested, which is especially useful with urgent
    interrupts while processing an exception.

    The implementation counts up the nesting level with each call to an
    exception. In the outer exception (level 1), the exception stack is
    started. All nested exceptions just reserve the redzone (scratch
    memory that may be used by compiler) and exception context on the
    stack, but then process on the same scratch.

    Restriction: Impure pointers are shared among all exceptions. This may
    be solved by creating an impure data structure in the stack frame with
    each nested exception.

       * or1k/crt0.S: Add exception nesting
       * or1k/exceptions-asm.S: ditto
       * or1k/util.c: ditto
2015-08-07 15:02:03 -04:00
Jeff Johnston 0d04c03829 or1k: Make heap end globally visible
Boards may change the initial value from _end to another value.

           * or1k/sbrk.c: Make heap end globally visible
2015-08-07 15:01:50 -04:00
Nick Clifton 9698cc0f33 This is part of a larger fix for RL78 complex relocs - they need an absolute symbol at address 0 that is not part of the *ABS* section.
* rl78/rl78-sim.ld: Provide a value for __rl78_abs__.
	* rl78/rl78.ld: Likewise.
2015-08-04 13:38:27 +01:00
Andre Simoes Dias Vieira c028685518 Change to nano.specs to add nano's include dir
Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2015-07-14 15:55:18 +02:00
Jeff Johnston bb5cb3afb5 or1k: Add missing initialization of impure ptr
* or1k/impure.c: Fix initialization of impure ptr
2015-05-27 13:30:20 +02:00
Jeff Johnston 5eb4a1666d or1k: set heap start for optimsoc-gzll
- With the gzll kernel we have two different loading options:

  - If the image is loaded to the global memory, the bootstrapping
    loads the kernel to local memory. Applications are loaded on
    demand. The heap then starts right after bss.

  - If the image is pre-loaded to the local memory it includes the
    application binaries right after bss. The heap then starts after
    the application objects.

- We can check if this is a gzll kernel as it has the string "gzll" at
  0x2000. At 0x200c we then find the end of the application objects in
  the image. If there is no global memory we set _or1k_heap_start to
  this value.

    * or1k/boards/optimsoc.S: Heap for gzll kernel
2015-05-27 13:30:20 +02:00
Jeff Johnston 58efeedd16 or1k: Make heap start configurable
- Previously the heap started right after the bss section. This can now
  be configured by changing the _or1k_heap_start symbol that defaults to
  the old value (&end). In board_init_early, we can now set this to
  another value.

    * or1k/sbrk.c: Allow for different heap start
2015-05-27 13:30:20 +02:00
Jeff Johnston aa26b78462 or1k: UART also accept timeout interrupt
- The UART interrupt only handled receiver FIFO full interrupts, but we
  also want to handle timeout interrupts.

    * or1k/or1k_uart.c: Fix interrupts
2015-05-27 13:30:20 +02:00
Jeff Johnston 58e5719a0e Bug fix in timer for or1k
- Properly set the interrupt pending flag in the timer mode register.

    * or1k/timer.c: Properly set interrupt flags
2015-05-27 13:30:20 +02:00
Jeff Johnston b46d3b5536 Store entire context for or1k
- Store the exception program counter (from EPCR) and exception status
  register (from ESR) also during the exception. A runtime system may
  replace them thereby to implement a thread switch.

    * or1k/exception-asm.S: Store missing state
2015-05-27 13:30:20 +02:00
Jeff Johnston a6342974b0 Fix exception stack frame for or1k
- We do not need a red zone here, as we do not operate on the current
  stack, but always use the clear exception stack. Also reserve two
  extra words for the context to store EPCR and ESR.

    * or1k/crt0.S: Fix exception stack frame
    * or1k/exception-asm.S: ditto
2015-05-27 13:30:19 +02:00
Jeff Johnston 132030fcf2 Fix interrupt handling for or1k.
- During interrupt handling the PICSR, table pointers and current
  interrupt line have been saved in incorrect registers and/or stored on
  the stack.

- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
  line in r22. Those are callee-saved registers, so that the register
  values will be preserved.

        * or1k/interruts-asm.S: Change registers to callee-saved.
2015-05-27 13:30:19 +02:00
Nick Clifton 324bd11706 Add a check that the data area does not overrun the stack.
* msp430/msp430-sim.ld (.stack): Add an assertion to make sure
	that the data area does not overrun the stack.  PROVIDE a new
	symbol __stack_size to allow the user to set the limit.
	* msp430/msp430xl-sim.ld (.stack): Likewise.
	* rl78/rl78-sim.ld (.stack): Likewise.
	* rl78/rl78.ld (.stack): Likewise.
	* rx/rx-sim.ld (.stack): Likewise.
	* rx/rx.ld (.stack): Likewise.
2015-05-27 13:30:19 +02:00
Nick Clifton baa681fd38 Adds support for placing MSP430 code and data into either low memory or high memory.
* msp430/msp430.ld: Delete.
	* msp430/msp430F5438A-l.ld: Delete.
	* msp430/msp430F5438A-s.ld: Delete.
	* msp430/crt_movedata.S: Delete.

	* msp430/Makefile.in (SCRIPTS): Remove msp430.ld.
	(CRT_OBJS): Add crt_move_highdata.o.
	* msp430/memmodel.h (START_CRT_FUNC): New macro.
	(END_CRT_FUNC): New macro.
	(WEAK_DEF): New macro.
	* msp430/crt0.S: Use new macros.
	(move_highdata): New code to initialise the .data section if it is
	held in high memory.

	* msp430/msp430-sim.ld (.data): Add .either.data.
	(.rodata2): Move some read-only data sections here.
	(.text): Add .either.text.
	(.rodata): Add .either.rodata.
	(.bss): Add .either.bss.
	* msp430/msp430xl-sim.ld (MEMORY): Add HIROM.
	(.rodata2): Move some read-only data sections here.
	(.upper.data): New section.  Include notes about how to initialise
	it.
2015-05-27 13:30:19 +02:00
Mike Frysinger e6101f3008 libgloss: mcore: add custom syscall header
The mcore simulator has a unique set of syscall numbers.  Add a header
that matches reality since the common one doesn't.
2015-04-23 22:03:45 +02:00
Mike Frysinger 6803327326 libgloss: arm: fix copy & paste in syscall.h
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
2015-04-23 22:03:45 +02:00