Added OverClocking features - Internal tests
This commit is contained in:
parent
2891fec236
commit
7fe45ef260
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@ -11,6 +11,7 @@ find_package(Gint 2.1 REQUIRED)
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set(SOURCES
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src/main.c
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src/clock.c
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# ...
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)
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# Shared assets, fx-9860G-only assets and fx-CG-50-only assets
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7
Demo.cbp
7
Demo.cbp
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@ -11,10 +11,17 @@
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<Option object_output="obj/Release/" />
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<Option type="1" />
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<Option compiler="null" />
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<Compiler>
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<Add directory="src" />
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</Compiler>
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</Target>
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</Build>
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<Unit filename="CMakeLists.txt" />
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<Unit filename="assets-cg/fxconv-metadata.txt" />
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<Unit filename="src/clock.c">
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<Option compilerVar="CC" />
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</Unit>
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<Unit filename="src/clock.h" />
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<Unit filename="src/main.c">
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<Option compilerVar="CC" />
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</Unit>
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16
Demo.layout
16
Demo.layout
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@ -2,19 +2,19 @@
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<CodeBlocks_layout_file>
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<FileVersion major="1" minor="0" />
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<ActiveTarget name="Release" />
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<File name="assets-cg/fxconv-metadata.txt" open="1" top="0" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<File name="CMakeLists.txt" open="1" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor>
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<Cursor1 position="278" topLine="0" />
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<Cursor1 position="613" topLine="0" />
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</Cursor>
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</File>
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<File name="assets-cg/fxconv-metadata.txt" open="1" top="1" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor>
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<Cursor1 position="324" topLine="0" />
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</Cursor>
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</File>
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<File name="src/main.c" open="1" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor>
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<Cursor1 position="24576" topLine="1006" />
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</Cursor>
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</File>
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<File name="CMakeLists.txt" open="1" top="1" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor>
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<Cursor1 position="902" topLine="8" />
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<Cursor1 position="394" topLine="0" />
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</Cursor>
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</File>
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</CodeBlocks_layout_file>
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@ -0,0 +1,304 @@
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#include "clock.h"
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#include <gint/hardware.h>
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#include <gint/defs/types.h>
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#define FLLFRQ_default 0x00004384
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#define FRQCR_default 0x0F011112
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#define CS0BCR_default 0x36DA0400 // CG50
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#define CS2BCR_default 0x36DA3400 // CG50
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#define CS3BCR_default 0x36DB4400 // CG50
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#define CS4BCR_default 0x36DB0400
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#define CS5aBCR_default 0x17DF0400
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#define CS5bBCR_default 0x17DF0400
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#define CS6aBCR_default 0x34D30200
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#define CS6bBCR_default 0x34D30200
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#define CS0WCR_default 0x000003C0 // CG50
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#define CS2WCR_default 0x000003C0 // CG50
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#define CS3WCR_default 0x000024D1 // CG50
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#define CS4WCR_default 0x00000540
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#define CS5aWCR_default 0x000203C1
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#define CS5bWCR_default 0x000203C1
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#define CS6aWCR_default 0x000302C0
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#define CS6bWCR_default 0x000302C0
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#define SDCR_default 0x00000A08
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#define PLL_32x 0b011111 //
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#define PLL_26x 0b011001 //
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#define PLL_16x 0b001111 // default
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#define DIV_2 0b0000 // 1/2
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#define DIV_4 0b0001 // 1/4
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#define DIV_8 0b0010 // 1/8
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#define DIV16 0b0011 // 1/16
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#define SLYDEBUG 0
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#if (SLYDEBUG==1)
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#include <gint/usb.h>
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#include <gint/usb-ff-bulk.h>
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#endif
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struct st_cpg {
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union { // struct FRQCRA similar to SH7724
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unsigned long LONG; // long Word Access
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struct { // Bit Access
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unsigned long KICK :1; // KICK
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unsigned long :1; //
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unsigned long STC :6; // STC
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unsigned long IFC :4; // IFC
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unsigned long :4; //
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unsigned long SFC :4; // SFC
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unsigned long BFC :4; // BFC
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unsigned long :4; //
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unsigned long PFC :4; // PFC
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} BIT;
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} FRQCRA;
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unsigned long FRQCRB; // 0xA41500004
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unsigned long FCLKACR; // 0xA41500008
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unsigned long FCLKBCR; // 0xA4150000C
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unsigned long unknownA41500010;
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unsigned long unknownA41500014;
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unsigned long IRDACLKCR; // 0xA41500018
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unsigned long unknownA4150001C;
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unsigned long unknownA41500020;
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unsigned long PLLCR; // 0xA41500024
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unsigned long unknownA41500028;
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unsigned long unknownA4150002C;
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unsigned long unknownA41500030;
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unsigned long unknownA41500034;
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unsigned long unknownA41500038;
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unsigned long SPUCLKCR; // 0xA4150003C
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unsigned long unknownA41500040;
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unsigned long unknownA41500044;
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unsigned long VCLKCR; // 0xA41500048
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unsigned long unknownA4150004C;
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union { // struct FLLFRQ similar to SH7724
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unsigned long LONG; // long Word Access
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struct { // Bit Access
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unsigned long :16; //
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unsigned long SELXM:2; // SELXM
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unsigned long :3; //
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unsigned long FLF :11; // FLF
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} BIT;
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} FLLFRQ;
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unsigned long unknownA41500054;
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unsigned long unknownA41500058;
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unsigned long unknownA4150005C;
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unsigned long LSTATS;
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};
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#define CPG (*(volatile struct st_cpg *)0xA4150000)
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uint32_t *FRQCR = (uint32_t*)0xA4150000;
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//uint32_t *FSICLKCR = (uint32_t*)0xA4150008;
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//uint32_t *DDCLRCR = (uint32_t*)0xA4150010;
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//uint32_t *USBCLKCR = (uint32_t*)0xA4150014;
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//uint32_t *PLL1CR = (uint32_t*)0xA4150024;
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//uint32_t *PLL2CR = (uint32_t*)0xA4150028;
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//uint32_t *SPUCLKCR = (uint32_t*)0xA415003C;
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//uint32_t *SSCGCR = (uint32_t*)0xA4150044;
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uint32_t *FLLFRQ = (uint32_t*)0xA4150050;
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//uint32_t *LSTATS = (uint32_t*)0xA4150060;
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//uint32_t *CMNCR = (uint32_t*)0xFEC10000;
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uint32_t *CS0BCR = (uint32_t*)0xFEC10004;
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uint32_t *CS2BCR = (uint32_t*)0xFEC10008;
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uint32_t *CS3BCR = (uint32_t*)0xFEC1000C;
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uint32_t *CS4BCR = (uint32_t*)0xFEC10010;
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uint32_t *CS5ABCR = (uint32_t*)0xFEC10014;
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uint32_t *CS5BBCR = (uint32_t*)0xFEC10018;
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uint32_t *CS6ABCR = (uint32_t*)0xFEC1001C;
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uint32_t *CS6BBCR = (uint32_t*)0xFEC10020;
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uint32_t *CS0WCR = (uint32_t*)0xFEC10024;
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uint32_t *CS2WCR = (uint32_t*)0xFEC10028;
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uint32_t *CS3WCR = (uint32_t*)0xFEC1002C;
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uint32_t *CS4WCR = (uint32_t*)0xFEC10030;
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uint32_t *CS5AWCR = (uint32_t*)0xFEC10034;
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uint32_t *CS5BWCR = (uint32_t*)0xFEC10038;
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uint32_t *CS6AWCR = (uint32_t*)0xFEC1003C;
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uint32_t *CS6BWCR = (uint32_t*)0xFEC10040;
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uint32_t *SDCR = (uint32_t*)0xFEC10044;
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uint32_t *RTCSR = (uint32_t*)0xFEC10048;
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uint32_t *RTCNT = (uint32_t*)0xFEC1004C;
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uint32_t *RTCOR = (uint32_t*)0xFEC10050;
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uint8_t *SDMR2 = (uint8_t*)0xFEC14000;
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uint8_t *SDMR3 = (uint8_t*)0xFEC15000;
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uint32_t SaveDataF0_FLLFRQ=FLLFRQ_default; // FLL:900 default
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uint32_t SaveDataF0_FRQCR =FRQCR_default; // PLL:x16 IFC:1/2 SFC:1/4 BFC:1/4 PFC:1/8
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uint32_t SaveDataF0_CS0BCR=CS0BCR_default; // IWW:4 IWRRS:4
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uint32_t SaveDataF0_CS2BCR=CS2BCR_default; // IWW:4 IWRRS:4
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uint32_t SaveDataF0_CS0WCR=CS0WCR_default; // wait:8
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uint32_t SaveDataF0_CS2WCR=CS2WCR_default; //
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uint32_t SaveDataF0_CS3BCR=CS3BCR_default; // IWW:4 IWRRS:4
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uint32_t SaveDataF0_CS3WCR=CS3WCR_default; // CL:2
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uint32_t SaveDataF0_CS5aBCR=CS5aBCR_default; //
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uint32_t SaveDataF0_CS5aWCR=CS5aWCR_default; //
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uint32_t SaveDataF2_FLLFRQ=0x00004000+900; // FLL:900 59MHz like CG10/20
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uint32_t SaveDataF2_FRQCR =(PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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uint32_t SaveDataF2_CS0BCR=0x24920400; // IWW:2 IWRRS:2
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uint32_t SaveDataF2_CS2BCR=0x24923400; // IWW:2 IWRRS:2
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uint32_t SaveDataF2_CS0WCR=0x00000340; // wait:6
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uint32_t SaveDataF2_CS2WCR=CS2WCR_default; //
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uint32_t SaveDataF2_CS3BCR=0x24924400; // IWW:2 IWRRS:2
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uint32_t SaveDataF2_CS3WCR=CS3WCR_default; // CL:2
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uint32_t SaveDataF2_CS5aBCR=CS5aBCR_default; //
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uint32_t SaveDataF2_CS5aWCR=CS5aWCR_default; //
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uint32_t SaveDataF3_FLLFRQ=0x00004000+900; // FLL:900 95.8MHz
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uint32_t SaveDataF3_FRQCR =(PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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uint32_t SaveDataF3_CS0BCR=0x24920400; // IWW:2 IWRRS:2
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uint32_t SaveDataF3_CS2BCR=0x24923400; // IWW:2 IWRRS:2
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uint32_t SaveDataF3_CS0WCR=0x00000240; // wait:4
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uint32_t SaveDataF3_CS2WCR=CS2WCR_default; //
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uint32_t SaveDataF3_CS3BCR=0x24924400; // IWW:2 IWRRS:2
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uint32_t SaveDataF3_CS3WCR=CS3WCR_default; // CL:2
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uint32_t SaveDataF3_CS5aBCR=CS5aBCR_default; //
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uint32_t SaveDataF3_CS5aWCR=CS5aWCR_default; //
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uint32_t SaveDataF4_FLLFRQ=0x00004000+900; // FLL:900 236MHz
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uint32_t SaveDataF4_FRQCR =(PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16;
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uint32_t SaveDataF4_CS0BCR=0x24920400; // IWW:2 IWRRS:2
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uint32_t SaveDataF4_CS2BCR=0x24923400; // IWW:2 IWRRS:2
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uint32_t SaveDataF4_CS0WCR=0x000002C0; // wait:5
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uint32_t SaveDataF4_CS2WCR=CS2WCR_default; //
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uint32_t SaveDataF4_CS3BCR=0x24924400; // IWW:2 IWRRS:2
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uint32_t SaveDataF4_CS3WCR=CS3WCR_default; // CL:2
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uint32_t SaveDataF4_CS5aBCR=CS5aBCR_default; //
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uint32_t SaveDataF4_CS5aWCR=CS5aWCR_default; //
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uint32_t SaveDataF5_FLLFRQ=0x00004000+900; // FLL:900 191MHz
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uint32_t SaveDataF5_FRQCR =(PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8;
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uint32_t SaveDataF5_CS0BCR=0x24920400; // IWW:2 IWRRS:2
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uint32_t SaveDataF5_CS2BCR=0x24923400; // IWW:2 IWRRS:2
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uint32_t SaveDataF5_CS0WCR=0x00000440; // wait:10
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uint32_t SaveDataF5_CS2WCR=CS2WCR_default; //
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uint32_t SaveDataF5_CS3BCR=0x24924400; // IWW:2 IWRRS:2
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uint32_t SaveDataF5_CS3WCR=CS3WCR_default; // CL:2
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uint32_t SaveDataF5_CS5aBCR=CS5aBCR_default; //
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uint32_t SaveDataF5_CS5aWCR=CS5aWCR_default; //
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void SetOCDefault( void )
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{
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FLLFRQ[0] = SaveDataF0_FLLFRQ;
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FRQCR[0] = SaveDataF0_FRQCR;
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CS0BCR[0] = SaveDataF0_CS0BCR;
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CS0WCR[0] = SaveDataF0_CS0WCR;
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CS2BCR[0] = SaveDataF0_CS2BCR;
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CS2WCR[0] = SaveDataF0_CS2WCR;
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CS3BCR[0] = SaveDataF0_CS3BCR;
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CS3WCR[0] = SaveDataF0_CS3WCR;
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CS5ABCR[0] = SaveDataF0_CS5aBCR;
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CS5AWCR[0] = SaveDataF0_CS5aWCR;
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("MODE OC_Normal SET", 0);
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#endif // SLYDEBUG
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}
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void SetOCPtuneF2( void )
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{
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FLLFRQ[0] = SaveDataF2_FLLFRQ;
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FRQCR[0] = SaveDataF2_FRQCR;
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CS0BCR[0] = SaveDataF2_CS0BCR;
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CS0WCR[0] = SaveDataF2_CS0WCR;
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CS2BCR[0] = SaveDataF2_CS2BCR;
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CS2WCR[0] = SaveDataF2_CS2WCR;
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CS3BCR[0] = SaveDataF2_CS3BCR;
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CS3WCR[0] = SaveDataF2_CS3WCR;
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CS5ABCR[0] = SaveDataF2_CS5aBCR;
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CS5AWCR[0] = SaveDataF2_CS5aWCR;
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("MODE PTune_F2 SET", 0);
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#endif // SLYDEBUG
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}
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void SetOCPtuneF3( void )
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{
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FLLFRQ[0] = SaveDataF3_FLLFRQ;
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FRQCR[0] = SaveDataF3_FRQCR;
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CS0BCR[0] = SaveDataF3_CS0BCR;
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CS0WCR[0] = SaveDataF3_CS0WCR;
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CS2BCR[0] = SaveDataF3_CS2BCR;
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CS2WCR[0] = SaveDataF3_CS2WCR;
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CS3BCR[0] = SaveDataF3_CS3BCR;
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CS3WCR[0] = SaveDataF3_CS3WCR;
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CS5ABCR[0] = SaveDataF3_CS5aBCR;
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CS5AWCR[0] = SaveDataF3_CS5aWCR;
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("MODE PTune_F3 SET", 0);
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#endif // SLYDEBUG
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}
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void SetOCPtuneF4( void )
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{
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FLLFRQ[0] = SaveDataF4_FLLFRQ;
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FRQCR[0] = SaveDataF4_FRQCR;
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CS0BCR[0] = SaveDataF4_CS0BCR;
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CS0WCR[0] = SaveDataF4_CS0WCR;
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CS2BCR[0] = SaveDataF4_CS2BCR;
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CS2WCR[0] = SaveDataF4_CS2WCR;
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CS3BCR[0] = SaveDataF4_CS3BCR;
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CS3WCR[0] = SaveDataF4_CS3WCR;
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CS5ABCR[0] = SaveDataF4_CS5aBCR;
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CS5AWCR[0] = SaveDataF4_CS5aWCR;
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("MODE PTune_F4 SET", 0);
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#endif // SLYDEBUG
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}
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void SetOCPtuneF5( void )
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{
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FLLFRQ[0] = SaveDataF5_FLLFRQ;
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FRQCR[0] = SaveDataF5_FRQCR;
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CS0BCR[0] = SaveDataF5_CS0BCR;
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CS0WCR[0] = SaveDataF5_CS0WCR;
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CS2BCR[0] = SaveDataF5_CS2BCR;
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CS2WCR[0] = SaveDataF5_CS2WCR;
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CS3BCR[0] = SaveDataF5_CS3BCR;
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CS3WCR[0] = SaveDataF5_CS3WCR;
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CS5ABCR[0] = SaveDataF5_CS5aBCR;
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CS5AWCR[0] = SaveDataF5_CS5aWCR;
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("MODE PTune_F5 SET", 0);
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#endif // SLYDEBUG
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}
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void clock_overclock( overclock_level level )
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{
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if(gint[HWCALC] == HWCALC_FXCG50)
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{
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#if (SLYDEBUG==1)
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if (usb_is_open()) usb_fxlink_text("HARDWARE OK", 0);
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#endif // SLYDEBUG
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if (level == OC_Default) SetOCDefault();
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else if (level == OC_PtuneF2) SetOCPtuneF2();
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else if (level == OC_PtuneF3) SetOCPtuneF3();
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else if (level == OC_PtuneF4) SetOCPtuneF4();
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else if (level == OC_PtuneF5) SetOCPtuneF5();
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else SetOCDefault();
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CPG.FRQCRA.BIT.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0);
|
||||
}
|
||||
else return;
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef CLOCK_H
|
||||
#define CLOCK_H
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OC_Default = 0, // Default (118MHz)
|
||||
OC_PtuneF2 = 1, // 59MHz
|
||||
OC_PtuneF3 = 2, // 96MHz
|
||||
OC_PtuneF4 = 3, // 236MHz
|
||||
OC_PtuneF5 = 4 // 191MHz
|
||||
} overclock_level;
|
||||
|
||||
|
||||
void clock_overclock( overclock_level level );
|
||||
|
||||
|
||||
#endif // CLOCK_H
|
||||
17
src/main.c
17
src/main.c
|
|
@ -14,6 +14,8 @@
|
|||
|
||||
#define MAXHEIGHT 200
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
|
||||
bool stop = false;
|
||||
bool skip_intro = false;
|
||||
|
|
@ -1184,16 +1186,26 @@ static void get_minimum_inputs( void )
|
|||
if(keydown(KEY_7)) screenshot = true;
|
||||
|
||||
if(keydown(KEY_8)) record = !record;
|
||||
|
||||
/// TEST OC
|
||||
|
||||
if (keydown(KEY_1)) clock_overclock( OC_Default );
|
||||
if (keydown(KEY_2)) clock_overclock( OC_PtuneF2 );
|
||||
if (keydown(KEY_3)) clock_overclock( OC_PtuneF3 );
|
||||
if (keydown(KEY_4)) clock_overclock( OC_PtuneF4 );
|
||||
if (keydown(KEY_5)) clock_overclock( OC_PtuneF5 );
|
||||
}
|
||||
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
|
||||
usb_interface_t const *interfaces[] = { &usb_ff_bulk, NULL };
|
||||
usb_open(interfaces, GINT_CALL_NULL);
|
||||
|
||||
/// TEST OC
|
||||
clock_overclock( OC_Default );
|
||||
|
||||
srand( rtc_ticks() );
|
||||
|
||||
size_t size = image_size_profile( 2, DWIDTH, MAXHEIGHT);
|
||||
|
|
@ -1265,6 +1277,9 @@ int main(void)
|
|||
get_minimum_inputs();
|
||||
}
|
||||
|
||||
/// TEST OC
|
||||
clock_overclock( OC_Default );
|
||||
|
||||
//free( screen );
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue