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gint/src/kernel/inth.S

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Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/*
** gint:core:inth - Interrupt handlers
** This file only contains the entry points because the gates are managed
** by device drivers. Each driver will supply its own interrupt handler
** blocks depending on its configuration.
*/
kernel: mask interrupts during callbacks on fx-CG Manager The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means that we have to mask interrupts as on SH3.
2020-07-20 16:44:27 +02:00
#define CPP_ASM
#include <gint/hardware.h>
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
.global _gint_inth_7305
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
#ifdef FX9860G
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
.global _gint_inth_7705
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
#endif
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
.global _gint_inth_callback
dma: add a new driver to support r61524 Also add a power interface (without driving code) and switch toolchain because the previous sh4eb-nofpu-elf toolchain was not completely FPU-free.
2019-03-10 15:45:34 +01:00
.section .gint.blocks, "ax"
.align 4
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* Interrupt handlers
The .gint.blocks section consists of blocks of 32 bytes intended for mapping
into the VBR space (exception, TLB miss, and interrupt handlers). Each event
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
gate is linearly associated with a block number on SH4:
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
block_id = (event_code - 0x3c0) / 0x20
and associated with a compact block number on SH3 through a table (to ensure
that blocks are consecutive in memory).
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
This file provides entry points; drivers may provide their own interrupt
handlers, and store them in the .gint.blocks section for consistency. They
should be aware of the consequences of reordering the blocks into the VBR
space:
- It is possible to map MPU-specific blocks at runtime, to avoid checking
the MPU each time an interrupt is handled;
way too much, including bopti/topti, timers, and more.
2019-02-21 20:58:38 +01:00
- However, the blocks can only rely on relative displacements or cross-
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
references if their relative order is known and heeded for both on SH4 and
SH3. A good example of this is the timer driver. Please be careful. */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
/* SH7305-TYPE DEBUG INTERRUPT HANDLER - 26 BYTES */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
#if 0
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
_gint_inth_7305:
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
mov.l 1f, r0
mov.l @r0, r4
sts.l pr, @-r15
mov.l 2f, r0
jsr @r0
nop
lds.l @r15+, pr
rte
nop
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
.zero 6
2: .long _debug
1: .long 0xff000028
#endif
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
/* SH7305-TYPE INTERRUPT HANDLER ENTRY - 40 BYTES */
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
_gint_inth_7305:
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
/* Save caller-saved registers which might currently be in use by the
interrupted function, as we don't know what the callback will do */
sts.l pr, @-r15
stc.l gbr, @-r15
sts.l mach, @-r15
sts.l macl, @-r15
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
/* Get the event code from the INTEVT register */
mov.l 1f, r0
mov.l @r0, r0
/* Interrupt codes start at 0x400 */
mov #4, r1
shll8 r1
sub r1, r0
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
/* Add the distance to the first entry and jump as a subroutine */
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
add #(.first_entry - .jump_over), r0
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
bsrf r0
nop
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
.jump_over:
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
/* Restore caller-saved registers */
lds.l @r15+, macl
lds.l @r15+, mach
ldc.l @r15+, gbr
lds.l @r15+, pr
rte
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
nop
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
.zero 24
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
1: .long 0xff000028
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
.first_entry:
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
#ifdef FX9860G
Add HWCALC entry for fx-9860G Slim
2022-09-25 04:48:07 +02:00
/* SH7705-TYPE INTERRUPT HANDLER ENTRY - 56 BYTES */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
_gint_inth_7705:
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
/* Save caller-saved registers as before */
sts.l pr, @-r15
stc.l gbr, @-r15
sts.l mach, @-r15
sts.l macl, @-r15
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* Get the event code from the INTEVT2 register */
mov.l 1f, r0
mov.l @r0, r0 /* r0 = old_code */
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
/* Translate the event code to compact format. The compact format is
laid out in a way that leaves no gap in the VBR space. Additionally,
gates are installed starting at VBR + 0x200 to save space. */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
mov.l 2f, r2
mov #-5, r3
shld r3, r0 /* r0 = old_code >> 5 */
add #-32, r0 /* r0 = (old_code - 0x400) >> 5 */
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
mov.b @(r0, r2), r0 /* r0 = gate_number */
add #16, r0 /* r0 = (0x200 + gate_number * 0x20) >> 5 */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
mov #5, r3
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
shld r3, r0 /* r0 = 0x200 + gate_number * 0x20 */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
/* Start at VBR + 0x200 and jump! */
stc vbr, r1
add r1, r0
jsr @r0
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
nop
/* Restore saved registers */
lds.l @r15+, macl
kernel: fix incorrect interrupt save/restore for MAC on SH3
2021-11-25 14:02:04 +01:00
lds.l @r15+, mach
interrupts: save caller-saved registers in main handler This is an obvious requirement for the interrupt routine, which was forgotten and only surfaced when I used a timer callback started with multiplications in an innocent add-in. r0..r7 are saved automatically, which leaves pr, gbr, mach et macl susceptible to corruption by the interrupt handler.
2020-05-06 16:37:44 +02:00
ldc.l @r15+, gbr
lds.l @r15+, pr
rte
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
nop
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
.zero 8
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
1: .long 0xa4000000 /* INTEVT2 register */
2: .long _inth_remap
remove the .gint.data section Since both platforms now have their VBR and gint-specific data loaded along the add-in's data, the .gint.data section is entirely unused. The .gint.bss section is still used for uninitialized objects (it has different semantics than .bss which is initially cleared) and the .gint.data.sh3 and .gint.bss.sh3 sections that are dropped on the SH4-only fx-CG 50 are also still used.
2020-07-10 16:36:05 +02:00
.data
dma: add a new driver to support r61524 Also add a power interface (without driving code) and switch toolchain because the previous sh4eb-nofpu-elf toolchain was not completely FPU-free.
2019-03-10 15:45:34 +01:00
.align 4
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
kernel: compact VBR scheme on SH3 I have recenty discovered that the so-called "rram" section used by gint to store its VBR space and a couple memory structures gets overwritten when returning to the main menu. It is thus necessary to get rid of it and store that data somewhere else. My current lead is to have it at the start of the static RAM by querying its address in the TLB. However, the static RAM is very small on SH3 (8k) so the VBR must be made more compact. This change elaborates the event code translation scheme used on SH3 to emulate SH4 event codes. It is now used to translate the event codes to a gint-specific VBR layout that leaves no gaps and thus reduces the size of the VBR space. The gint_inthandler() method has to be modified for every new SH3 interrupt to maintain this scheme.
2020-07-09 10:32:53 +02:00
/* EVENT CODE TRANSLATION TABLE - 96 BYTES
This table was originally used to translate SH3 event codes to corresponding
SH4 events codes so that the VBR can be laid out in the SH4 model on every
platform. However, due to memory size limitations on SH3, it now also
translates SH4 event codes to adjacent gates numbers to reduce the size of
the VBR section.
The VBR interrupt space on SH3 is laid out as follows:
VBR offset SH3 events Description
rtc: robust interrupt handling and SH3 compatibility This commit changes the interrupt handler arrangement to support the PRI interrupt on SH3 (a gap is needed between 0xaa0 and its helper). It also introduces the use of the _gint_inth_callback function for the callback, which provides dynamic TLB during the interrupt, and revealed a bug about IMASK not being set automatically on SH3. Finally, it sets the interrupt settings of the RTC more conservatively, by wiping RCR1 and the carry, alarm and periodic interrupt flags during initialization and context restoration.
2020-07-19 20:06:50 +02:00
-------------------------------------------------------------------
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
0x200 400 420 440 TMU0, TMU1, TMU2
0x260 f00 --- --- --- ETMU0, 3-gate logic at ETMU4
0x2e0 4a0 RTC Periodic Interrupt
rtc: robust interrupt handling and SH3 compatibility This commit changes the interrupt handler arrangement to support the PRI interrupt on SH3 (a gap is needed between 0xaa0 and its helper). It also introduces the use of the _gint_inth_callback function for the callback, which provides dynamic TLB during the interrupt, and revealed a bug about IMASK not being set automatically on SH3. Finally, it sets the interrupt settings of the RTC more conservatively, by wiping RCR1 and the carry, alarm and periodic interrupt flags during initialization and context restoration.
2020-07-19 20:06:50 +02:00
-------------------------------------------------------------------
kernel: compact VBR scheme on SH3 I have recenty discovered that the so-called "rram" section used by gint to store its VBR space and a couple memory structures gets overwritten when returning to the main menu. It is thus necessary to get rid of it and store that data somewhere else. My current lead is to have it at the start of the static RAM by querying its address in the TLB. However, the static RAM is very small on SH3 (8k) so the VBR must be made more compact. This change elaborates the event code translation scheme used on SH3 to emulate SH4 event codes. It is now used to translate the event codes to a gint-specific VBR layout that leaves no gaps and thus reduces the size of the VBR space. The gint_inthandler() method has to be modified for every new SH3 interrupt to maintain this scheme.
2020-07-09 10:32:53 +02:00
0x600 --- --- Entry gate
rtc: robust interrupt handling and SH3 compatibility This commit changes the interrupt handler arrangement to support the PRI interrupt on SH3 (a gap is needed between 0xaa0 and its helper). It also introduces the use of the _gint_inth_callback function for the callback, which provides dynamic TLB during the interrupt, and revealed a bug about IMASK not being set automatically on SH3. Finally, it sets the interrupt settings of the RTC more conservatively, by wiping RCR1 and the carry, alarm and periodic interrupt flags during initialization and context restoration.
2020-07-19 20:06:50 +02:00
-------------------------------------------------------------------
kernel: compact VBR scheme on SH3 I have recenty discovered that the so-called "rram" section used by gint to store its VBR space and a couple memory structures gets overwritten when returning to the main menu. It is thus necessary to get rid of it and store that data somewhere else. My current lead is to have it at the start of the static RAM by querying its address in the TLB. However, the static RAM is very small on SH3 (8k) so the VBR must be made more compact. This change elaborates the event code translation scheme used on SH3 to emulate SH4 event codes. It is now used to translate the event codes to a gint-specific VBR layout that leaves no gaps and thus reduces the size of the VBR space. The gint_inthandler() method has to be modified for every new SH3 interrupt to maintain this scheme.
2020-07-09 10:32:53 +02:00
kernel: compact VBR even more on SH3 This change moves interrupt handler from VBR + 0x640 to VBR + 0x200, in the gap between the exception and TLB miss handlers. This new scheme is not limited to VBR+0x200 .. VBR+0x400 as new large block numbers can be used to jump over the TLB miss handler and the interrupt handler entry points.
2020-07-10 13:07:12 +02:00
There is space for 16 gates at VBR + 0x200 so the VBR currently ends after
the interrupt entry gate at VBR + 0x640. */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
_inth_remap:
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
.byte 0, 1, 2, 0xff, 0xff, 7, 0xff, 0xff
kernel: compact VBR scheme on SH3 I have recenty discovered that the so-called "rram" section used by gint to store its VBR space and a couple memory structures gets overwritten when returning to the main menu. It is thus necessary to get rid of it and store that data somewhere else. My current lead is to have it at the start of the static RAM by querying its address in the TLB. However, the static RAM is very small on SH3 (8k) so the VBR must be made more compact. This change elaborates the event code translation scheme used on SH3 to emulate SH4 event codes. It is now used to translate the event codes to a gint-specific VBR layout that leaves no gaps and thus reduces the size of the VBR space. The gint_inthandler() method has to be modified for every new SH3 interrupt to maintain this scheme.
2020-07-09 10:32:53 +02:00
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
.byte 3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
#endif
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
.section .gint.mapped, "ax"
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
/* CALLBACK HELPER
This function implements the callback with context saving. It is a general
function and does not need to reside in VBR space which is block-structured.
This function saves registers r0_bank...r7_bank, enables interrupts,
switches back to user bank and executes the callback. It does not save other
registers (pr/mach/macl/gbr) which are managed by the handler entry. */
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
/* gint_inth_callback: Indirect call from kernel space to userland
@r4 Address of callback function
-> Returns the return value of the callback (int). */
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
_gint_inth_callback_reloc:
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
stc.l r0_bank, @-r15
stc.l r1_bank, @-r15
stc.l r2_bank, @-r15
stc.l r3_bank, @-r15
stc.l r4_bank, @-r15
stc.l r5_bank, @-r15
stc.l r6_bank, @-r15
stc.l r7_bank, @-r15
stc.l spc, @-r15
stc.l ssr, @-r15
stc.l sr, @-r15
core tmu: improve reliability of interrupt handlers This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
/* Save some values to user bank; once we enable interrupts, the kernel
bank might be overwritten at any moment. */
ldc r4, r0_bank
kernel: mask interrupts during callbacks on SH3! This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
/* Enable interrupts and go back to user bank. On SH4, SR.IMASK is set
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
to the level of the current interrupt, which makes sure we can only
be re-interrupted by something with a higher priority. */
kernel: mask interrupts during callbacks on SH3! This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
stc sr, r1
mov.l .SR_clear_RB_BL, r0
and r0, r1
kernel: mask interrupts during callbacks on fx-CG Manager The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means that we have to mask interrupts as on SH3.
2020-07-20 16:44:27 +02:00
/* On SH3 the CPUOPM.INTMU bit is not supported, and on the fx-CG
emulator, it is outright ignored. In these situations, set IMASK to
15 to block interrupts while allowing TLB misses to be handled. */
mov.l .gint, r2
mov.l @r2, r0
kernel: mask interrupts during callbacks on SH3! This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
tst #1, r0
kernel: mask interrupts during callbacks on fx-CG Manager The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means that we have to mask interrupts as on SH3.
2020-07-20 16:44:27 +02:00
bf .set_imask
mov.l @(4*HWCALC,r2), r0
cmp/eq #HWCALC_FXCG_MANAGER, r0
bt .set_imask
bra .load_sr
nop
.set_imask:
kernel: mask interrupts during callbacks on SH3! This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
mov.l .SR_set_IMASK, r0
or r0, r1
.load_sr:
ldc r1, sr
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
/* We are now in the user bank with r0 set. Perform the call. We want
core tmu: improve reliability of interrupt handlers This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
to forward the return value to kernel bank, but this bank can be
changed at any moment since interrupts are enabled. */
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
sts.l pr, @-r15
use GINT_CALL() in every API that has callbacks * Change gint_inth_callback() * Add intc_handler_function() to use C functions as handlers instead of writing assembler, and use it in the RTC and USB * Revisit the TMU handlers, which after moving out the callbacks, now fit into 3 gates (great!), and adapt the ETMU handler * Improve the timer driver (less code = better code, removed magic constants assuming the VBR layout on SH3/SH4, etc.) * Remove 2 gates and a gap from the compact scheme on SH3 * Define timer_configure() to replace timer_setup(), which could not be cleanly updated to support GINT_CALL() * Replace rtc_start/stop_timer with rtc_periodic_enable/disable, which is less confusing because of ETMU being "RTC timers"
2021-04-27 14:29:38 +02:00
mov.l @(4, r0), r4
mov.l @(8, r0), r5
mov.l @(12, r0), r6
mov.l @(16, r0), r7
mov.l @r0, r0
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
jsr @r0
core tmu: improve reliability of interrupt handlers This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
nop
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
lds.l @r15+, pr
/* Restore the previous status register and the registers of the
core tmu: improve reliability of interrupt handlers This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
interrupted procedure. Restoring sr gets us back to system bank with
interrupts disabled. */
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
ldc.l @r15+, sr
core tmu: improve reliability of interrupt handlers This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
2020-06-20 09:32:48 +02:00
/* We can now pull the return value since interrupts are disabled */
stc r0_bank, r0
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
ldc.l @r15+, ssr
ldc.l @r15+, spc
ldc.l @r15+, r7_bank
ldc.l @r15+, r6_bank
ldc.l @r15+, r5_bank
ldc.l @r15+, r4_bank
ldc.l @r15+, r3_bank
ldc.l @r15+, r2_bank
ldc.l @r15+, r1_bank
rts
ldc.l @r15+, r0_bank
.align 4
.SR_clear_RB_BL:
.long ~((1 << 29) | (1 << 28))
kernel: mask interrupts during callbacks on SH3! This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
2020-07-19 20:02:50 +02:00
.SR_set_IMASK:
.long (0xf << 4)
.gint:
.long _gint
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
.section .gint.mappedrel, "aw"
_gint_inth_callback:
.long _gint_inth_callback_reloc