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Clean but still some bugs with SH3

This commit is contained in:
Sylvain PILLOT 2022-12-06 18:48:44 +01:00
parent d013bcdd20
commit 9b7951c3a2
2 changed files with 3 additions and 13 deletions
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12
src/cpg/cpg.c
View File

@ -26,10 +26,7 @@ const clock_frequency_t *clock_freq(void)
// SH7705 Clock signals
//---
//#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
//#define CPGSH3 SH7705_CPG
void sh7705_probe(void)
static void sh7705_probe(void)
{
/* According to Sentaro21 in the sources of Ftune 1.0.1, the clock mode
is thought to be 5, which means that:
@ -69,15 +66,11 @@ void sh7705_probe(void)
freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
}
//#undef CPG
//#endif /* FX9860G and platform-agnostic */
//---
// SH7305 clock signals
//---
//#define CPGSH4 SH7305_CPG
static void sh7305_probe(void)
{
/* The meaning of the PLL setting on SH7305 differs from the
@ -113,9 +106,6 @@ static void sh7305_probe(void)
freq.Pphi_f = base >> (divp + 1);
}
//#undef CPG
//---
// Initialization
//---

4
src/cpg/overclock.c
View File

@ -99,8 +99,8 @@ void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
if(isSH3())
{
SH7705_WDT.WTCNT.WRITE = 0;
SH7705_WDT.WTCNT.WRITE = 0x65;
SH7705_CPG.FRQCR.word = 0x1000 | (uint16_t) s->FRQCR;
SH7705_WDT.WTCSR.WRITE = 0x65;
SH7705_CPG.FRQCR.word = (uint16_t) (0x1000 | ((uint16_t) s->FRQCR));
SH7705_BSC.CS0BCR.lword = s->CS0BCR;
SH7705_BSC.CS0WCR.lword = s->CS0WCR;
SH7705_BSC.CS2BCR.lword = s->CS2BCR;