Overclock support for all SH3 and SH4 calculators supported by Gint/fxSDk : Fx9860Gs and fxCGs #23
|
|
@ -65,6 +65,8 @@ void cpg_compute_freq(void);
|
|||
gint. These are always the settings from Ftune/Ptune, which are the most
|
||||
widely tested and gint treats as the standard. */
|
||||
enum {
|
||||
/* Something went wrong during the overclocking process*/
|
||||
CLOCK_ERROR = 99,
|
||||
/* Combinations of hardware settings that are none of Ftune's levels */
|
||||
CLOCK_SPEED_UNKNOWN = 0,
|
||||
|
||||
|
|
@ -72,12 +74,16 @@ enum {
|
|||
thoug many more are involved.
|
||||
|
||||
On SH4 fx-9860G-likr:
|
||||
(Not supported yet)
|
||||
(Not tested yet)
|
||||
|
||||
On the fx G-III series:
|
||||
(Not supported yet)
|
||||
On the fx 9860G-II series: (taken from Sentaro21's README)
|
||||
F1: CPU @ 29 MHz, BFC @ 29 MHz [Default speed]
|
||||
F2: CPU @ 58 MHz, BFC @ 29 MHz [Same as fx-CG10/20]
|
||||
F3: CPU @ 29 MHz, BFC @ 29 MHz [Same as SH3]
|
||||
F4: CPU @ 118 MHz, BFC @ 59 MHz [Fastest CPU option]
|
||||
F5: CPU @ 236 MHz, BFC @ 118 MHz [Fastest CPU option]
|
||||
|
||||
On fx-CG 10/20:
|
||||
On fx-CG 10/20:
|
||||
F1: CPU @ 58 MHz, BFC @ 29 MHz [Default speed]
|
||||
F2: CPU @ 58 MHz, BFC @ 29 MHz [Improved memory speed]
|
||||
F3: CPU @ 118 MHz, BFC @ 58 MHz [Faster than F2]
|
||||
|
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@ -100,7 +106,6 @@ enum {
|
|||
CLOCK_SPEED_DEFAULT = CLOCK_SPEED_F1,
|
||||
};
|
||||
|
||||
#ifdef FXCG50
|
||||
/* clock_get_speed(): Determine the current clock speed
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||||
|
||||
This function compares the current hardware state with the settings for each
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||||
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|
@ -108,6 +113,10 @@ enum {
|
|||
correspond to any of Ftune's settings, CLOCK_SPEED_UNKNOWN is returned. */
|
||||
int clock_get_speed(void);
|
||||
|
||||
void clock_save_state(void);
|
||||
|
||||
void clock_restore_state(void);
|
||||
|
||||
/* clock_set_speed(): Set the current clock speed
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||||
|
||||
This function sets the clock speed to the desired level. This is "the
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||||
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@ -123,7 +132,6 @@ int clock_get_speed(void);
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|||
Currently the clock speed is not reset during a world switch nor when
|
||||
leaving the add-in. */
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||||
void clock_set_speed(int speed);
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||||
#endif
|
||||
|
||||
//---
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||||
// Sleep functions
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||||
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|
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|||
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@ -12,6 +12,84 @@ extern "C" {
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|||
#include <gint/defs/attributes.h>
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||||
#include <gint/defs/types.h>
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||||
|
||||
//---
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||||
// SH7705 But State Controller. Refer to:
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||||
// Renesas SH7705 Group Hardware Manual
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||||
// Section 7: Bus State Controller (BSC)
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||||
//---
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||||
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||||
typedef volatile lword_union(sh7705_bsc_CSnBCR_t,
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||||
uint32_t :2;
|
||||
uint32_t IWW :2;
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||||
uint32_t :1;
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||||
uint32_t IWRWD :2;
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||||
uint32_t :1;
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||||
uint32_t IWRWS :2;
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||||
uint32_t :1;
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||||
uint32_t IWRRD :2;
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||||
uint32_t :1;
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||||
uint32_t IWRRS :2;
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||||
uint32_t :1;
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||||
uint32_t TYPE :3;
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||||
uint32_t :1;
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||||
uint32_t BSZ :2;
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||||
uint32_t :9;
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||||
);
|
||||
|
||||
typedef volatile lword_union(sh7705_bsc_CSnWCR_t,
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||||
uint32_t :13;
|
||||
uint32_t WW :3;
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||||
uint32_t :3;
|
||||
uint32_t SW :2;
|
||||
uint32_t WR :4;
|
||||
uint32_t WM :1;
|
||||
uint32_t :4;
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||||
uint32_t HW :2;
|
||||
);
|
||||
|
||||
|
||||
typedef volatile struct
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||||
{
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||||
lword_union(CMNCR,
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||||
uint32_t :24; /* reserved */
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||||
uint32_t DMAIW : 2; /* Wait State*/
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||||
uint32_t DMAIWA : 1; /* Method of Inserting Wait state bewteen cycles */
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||||
uint32_t :1; /* reserved */
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||||
uint32_t ENDIAN : 1; /* Endian Flag*/
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||||
uint32_t :1; /* reserved */
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||||
uint32_t HIZMEM : 1; /* High Z memory Control*/
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||||
uint32_t HIZCNT : 1; /* High Z Control*/
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||||
);
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||||
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||||
sh7705_bsc_CSnBCR_t CS0BCR;
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||||
sh7705_bsc_CSnBCR_t CS2BCR;
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||||
sh7705_bsc_CSnBCR_t CS3BCR;
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||||
sh7705_bsc_CSnBCR_t CS4BCR;
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||||
sh7705_bsc_CSnBCR_t CS5ABCR;
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||||
sh7705_bsc_CSnBCR_t CS5BBCR;
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||||
sh7705_bsc_CSnBCR_t CS6ABCR;
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||||
sh7705_bsc_CSnBCR_t CS6BBCR;
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||||
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||||
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||||
sh7705_bsc_CSnWCR_t CS0WCR;
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||||
sh7705_bsc_CSnWCR_t CS2WCR;
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||||
sh7705_bsc_CSnWCR_t CS3WCR;
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||||
sh7705_bsc_CSnWCR_t CS4WCR;
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||||
sh7705_bsc_CSnWCR_t CS5AWCR;
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||||
sh7705_bsc_CSnWCR_t CS5BWCR;
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||||
sh7705_bsc_CSnWCR_t CS6AWCR;
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||||
sh7705_bsc_CSnWCR_t CS6BWCR;
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||||
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||||
/* TODO : there are several other registers not described yet
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||||
as they are not used for overclocking the SH7705 processor.
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||||
To be done later on when needed.*/
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||||
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||||
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||||
} GPACKED(4) sh7705_bsc_t;
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||||
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||||
#define SH7705_BSC (*(sh7705_bsc_t *)0xa4fd0000)
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||||
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||||
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||||
//---
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||||
// SH7305 But State Controller. Refer to:
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||||
// Renesas SH7730 Group Hardware Manual
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||||
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@ -31,6 +31,12 @@ typedef volatile struct
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|||
uint16_t :2;
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||||
uint16_t PFC :2; /* Peripheral clock divider */
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||||
);
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||||
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||||
byte_union(UCLKCR,
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||||
uint8_t USSCS :2; /* Source Clock Selection Bit*/
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||||
uint8_t USBEN :1; /* USB On-Chip Oscillator Enable*/
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||||
uint8_t :5; /* reserved */
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||||
);
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||||
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||||
} GPACKED(4) sh7705_cpg_t;
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||||
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||||
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@ -79,6 +79,199 @@ typedef volatile struct
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|||
// TODO: Document the SH7305 Pin Function Controller
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||||
//---
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||||
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||||
typedef volatile word_union( sh7305_Port_Control_Register_t,
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||||
uint16_t P7MD :2;
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||||
uint16_t P6MD :2;
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||||
uint16_t P5MD :2;
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||||
uint16_t P4MD :2;
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||||
uint16_t P3MD :2;
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||||
uint16_t P2MD :2;
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||||
uint16_t P1MD :2;
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||||
uint16_t P0MD :2;
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||||
);
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||||
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||||
typedef volatile byte_union( sh7305_port_data_register_t,
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||||
uint8_t P7DT :1;
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||||
uint8_t P6DT :1;
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||||
uint8_t P5DT :1;
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||||
uint8_t P4DT :1;
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||||
uint8_t P3DT :1;
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||||
uint8_t P2DT :1;
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||||
uint8_t P1DT :1;
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||||
uint8_t P0DT :1;
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||||
);
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||||
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||||
typedef volatile word_union( sh7305_pin_select_register_t,
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||||
uint16_t PS15 :1;
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||||
uint16_t PS14 :1;
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||||
uint16_t PS13 :1;
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||||
uint16_t PS12 :1;
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||||
uint16_t PS11 :1;
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||||
uint16_t PS10 :1;
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||||
uint16_t PS9 :1;
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||||
uint16_t PS8 :1;
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||||
uint16_t PS7 :1;
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||||
uint16_t PS6 :1;
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||||
uint16_t PS5 :1;
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||||
uint16_t PS4 :1;
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||||
uint16_t PS3 :1;
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||||
uint16_t PS2 :1;
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||||
uint16_t PS1 :1;
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||||
uint16_t PS0 :1;
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||||
);
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||||
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||||
typedef volatile word_union( sh7305_IO_buffer_hiz_control_register_t,
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||||
uint16_t HIZ15 :1;
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||||
uint16_t HIZ14 :1;
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||||
uint16_t HIZ13 :1;
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||||
uint16_t HIZ12 :1;
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||||
uint16_t HIZ11 :1;
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||||
uint16_t HIZ10 :1;
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||||
uint16_t HIZ9 :1;
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||||
uint16_t HIZ8 :1;
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||||
uint16_t HIZ7 :1;
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||||
uint16_t HIZ6 :1;
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||||
uint16_t HIZ5 :1;
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||||
uint16_t HIZ4 :1;
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||||
uint16_t HIZ3 :1;
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||||
uint16_t HIZ2 :1;
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||||
uint16_t HIZ1 :1;
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||||
uint16_t HIZ0 :1;
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||||
);
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||||
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||||
typedef volatile word_union( sh7305_module_function_select_register_t,
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||||
uint16_t MSEL15 :1;
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||||
uint16_t MSEL14 :1;
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||||
uint16_t MSEL13 :1;
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||||
uint16_t MSEL12 :1;
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||||
uint16_t MSEL11 :1;
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||||
uint16_t MSEL10 :1;
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||||
uint16_t MSEL9 :1;
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||||
uint16_t MSEL8 :1;
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||||
uint16_t MSEL7 :1;
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||||
uint16_t MSEL6 :1;
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||||
uint16_t MSEL5 :1;
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||||
uint16_t MSEL4 :1;
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||||
uint16_t MSEL3 :1;
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||||
uint16_t MSEL2 :1;
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||||
uint16_t MSEL1 :1;
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||||
uint16_t MSEL0 :1;
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||||
);
|
||||
|
||||
typedef volatile word_union( sh7305_IO_buffer_drive_control_register_t,
|
||||
uint16_t DRV15 :1;
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||||
uint16_t DRV14 :1;
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||||
uint16_t DRV13 :1;
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||||
uint16_t DRV12 :1;
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||||
uint16_t DRV11 :1;
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||||
uint16_t DRV10 :1;
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||||
uint16_t DRV9 :1;
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||||
uint16_t DRV8 :1;
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||||
uint16_t DRV7 :1;
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||||
uint16_t DRV6 :1;
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||||
uint16_t DRV5 :1;
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||||
uint16_t DRV4 :1;
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||||
uint16_t DRV3 :1;
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||||
uint16_t DRV2 :1;
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||||
uint16_t DRV1 :1;
|
||||
uint16_t DRV0 :1;
|
||||
);
|
||||
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// List of all PORT CONTROL REGISTERS (PCRs)
|
||||
sh7305_Port_Control_Register_t PACR;
|
||||
sh7305_Port_Control_Register_t PBCR;
|
||||
sh7305_Port_Control_Register_t PCCR;
|
||||
sh7305_Port_Control_Register_t PDCR;
|
||||
sh7305_Port_Control_Register_t PECR;
|
||||
sh7305_Port_Control_Register_t PFCR;
|
||||
sh7305_Port_Control_Register_t PGCR;
|
||||
sh7305_Port_Control_Register_t PHCR;
|
||||
sh7305_Port_Control_Register_t PJCR;
|
||||
sh7305_Port_Control_Register_t PKCR;
|
||||
sh7305_Port_Control_Register_t PLCR;
|
||||
sh7305_Port_Control_Register_t PMCR;
|
||||
sh7305_Port_Control_Register_t PNCR;
|
||||
sh7305_Port_Control_Register_t PQCR;
|
||||
sh7305_Port_Control_Register_t PRCR;
|
||||
sh7305_Port_Control_Register_t PSCR;
|
||||
|
||||
// List of all PORT DATA REGISTERS (PDRs)
|
||||
sh7305_port_data_register_t PADR;
|
||||
sh7305_port_data_register_t PBDR;
|
||||
sh7305_port_data_register_t PCDR;
|
||||
sh7305_port_data_register_t PDDR;
|
||||
sh7305_port_data_register_t PEDR;
|
||||
sh7305_port_data_register_t PFDR;
|
||||
sh7305_port_data_register_t PGDR;
|
||||
sh7305_port_data_register_t PHDR;
|
||||
sh7305_port_data_register_t PJDR;
|
||||
sh7305_port_data_register_t PKDR;
|
||||
sh7305_port_data_register_t PLDR;
|
||||
sh7305_port_data_register_t PMDR;
|
||||
sh7305_port_data_register_t PNDR;
|
||||
sh7305_port_data_register_t PQDR;
|
||||
sh7305_port_data_register_t PRDR;
|
||||
sh7305_port_data_register_t PSDR;
|
||||
|
||||
sh7305_Port_Control_Register_t PTCR;
|
||||
sh7305_Port_Control_Register_t PUCR;
|
||||
sh7305_Port_Control_Register_t PVCR;
|
||||
|
||||
//Missing ports ?
|
||||
//sh7305_Port_Control_Register_t PWCR;
|
||||
//sh7305_Port_Control_Register_t PXCR;
|
||||
//sh7305_Port_Control_Register_t PYCR;
|
||||
//sh7305_Port_Control_Register_t PZCR;
|
||||
pad( 0x08 );
|
||||
|
||||
// List of all PIN SELECT REGISTERS (PSELs)
|
||||
sh7305_pin_select_register_t PSELA;
|
||||
sh7305_pin_select_register_t PSELB;
|
||||
sh7305_pin_select_register_t PSELC;
|
||||
sh7305_pin_select_register_t PSELD;
|
||||
sh7305_pin_select_register_t PSELE;
|
||||
|
||||
// List of all IO BUFFER HI-Z CONTROL REGISTERS (HIZCRs)
|
||||
sh7305_IO_buffer_hiz_control_register_t HIZCRA;
|
||||
sh7305_IO_buffer_hiz_control_register_t HIZCRB;
|
||||
sh7305_IO_buffer_hiz_control_register_t HIZCRC;
|
||||
|
||||
// the next one is not clearly listed, can be aither PSELF or HIZCRD so we skip it with pad
|
||||
//sh7305_pin_select_register_t PSELF;
|
||||
//sh7305_IO_buffer_hiz_control_register_t HIZCRD;
|
||||
pad( 0x02 );
|
||||
|
||||
sh7305_port_data_register_t PTDR;
|
||||
sh7305_port_data_register_t PUDR;
|
||||
sh7305_port_data_register_t PVDR;
|
||||
|
||||
//Missing ports ?
|
||||
//sh7305_port_data_register_t PWDR;
|
||||
//sh7305_port_data_register_t PXDR;
|
||||
//sh7305_port_data_register_t PYDR;
|
||||
//sh7305_port_data_register_t PZDR;
|
||||
pad( 0x08 );
|
||||
|
||||
|
||||
pad( 0x12 ); // jump from address 0xa405016e to 0xa4050180
|
||||
|
||||
|
||||
// List of all MODULE FUNCTION SELECT REGISTERS (MSELs)
|
||||
sh7305_module_function_select_register_t MSELCRA;
|
||||
sh7305_module_function_select_register_t MSELCRB;
|
||||
|
||||
|
||||
} sh7305_pfc_t;
|
||||
|
||||
#define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
//---
|
||||
// gint:mpu:scif - Serial Communication Interface with FIFO (SCIF)
|
||||
//---
|
||||
|
||||
#ifndef GINT_MPU_SCIF
|
||||
#define GINT_MPU_SCIF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <gint/defs/attributes.h>
|
||||
#include <gint/defs/types.h>
|
||||
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// Serial Mode
|
||||
word_union(SCSMR,
|
||||
uint16_t :8; //Reserved
|
||||
uint16_t CA :1; //Communication Mode.
|
||||
uint16_t CHR :1; //Character Length.
|
||||
uint16_t PE :1; //Parity Enable
|
||||
uint16_t OE :1; //Parity Mode
|
||||
uint16_t STOP :1; //Bit Stop Length
|
||||
uint16_t :1; //Reserved
|
||||
uint16_t CKS :2; //Clock Select
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial Bit Rate
|
||||
uint8_t SCBRR; //set the bit rate of serial transmission/reception in relation to the operating clock of the baud rate generator
|
||||
pad(0x3);
|
||||
|
||||
// Serial Control
|
||||
word_union(SCSCR,
|
||||
uint16_t :8; //Reserved
|
||||
uint16_t TIE :1; //Transmit Interrupt Enable
|
||||
uint16_t RIE :1; //Receive Interrupt Enable
|
||||
uint16_t TE :1; //Transmit Enable
|
||||
uint16_t RE :1; //Receive Mode
|
||||
uint16_t REIE :1; //Receive Error Interrupt Enable
|
||||
uint16_t :1; //Reserved
|
||||
uint16_t CKE :2; //Clock Enable
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial Transmit data
|
||||
uint8_t SCFTD; // FIFO for serial transmit data
|
||||
pad(0x3);
|
||||
|
||||
// Serial Status
|
||||
word_union(SCFSR,
|
||||
uint16_t PERC :4; //Number of Parity Errors
|
||||
uint16_t FERC :4; //Number of Framing Errors
|
||||
uint16_t ER :1; //Receive Error
|
||||
uint16_t TEND :1; //Transmit End
|
||||
uint16_t TDFE :1; //Transmit FIFO Data Empty
|
||||
uint16_t BRK :1; //Break Detection
|
||||
uint16_t FER :1; //Framing Error Indication
|
||||
uint16_t PER :1; //Parity Error Indication
|
||||
uint16_t RDF :1; //Receive FIFO Data Full
|
||||
uint16_t DR :1; //Received data Ready
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial Receive data
|
||||
uint8_t SCFRD; // FIFO for serial received data
|
||||
pad(0x3);
|
||||
|
||||
// Serial FIFO Control
|
||||
word_union(SCFCR,
|
||||
uint16_t :5; //Reserved
|
||||
uint16_t RSTRG :3; // ??? from CGplayer
|
||||
uint16_t RTRG :2; //Receive FIFO Data Trigger
|
||||
uint16_t TTRG :2; //Transmit FIFO Data Trigger
|
||||
uint16_t MCE :1; // ??? from CGplayer
|
||||
uint16_t TFRST :1; //Transmit FIFO Data Register Reset
|
||||
uint16_t RFRST :1; //Receive FIFO Data Register Reset
|
||||
uint16_t LOOP :1; //Loopback Test
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial FIFO Count
|
||||
word_union(SCFDR,
|
||||
uint16_t :3; //Reserved
|
||||
uint16_t TFDC :5; //Number of Data Bytes in Transmit FIFO
|
||||
uint16_t :3; //Reserved
|
||||
uint16_t RFDC :5; //Number of Data Bytes in Receive FIFO
|
||||
);
|
||||
pad(0x6);
|
||||
|
||||
// Serial Line Status
|
||||
word_union(SCLSR,
|
||||
uint16_t :15; //Reserved
|
||||
uint16_t ORER :1; //Overrun Error
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
} GPACKED(4) sh7305_scif_t;
|
||||
|
||||
#define SH7305_SCIF (*((sh7305_scif_t *)0xa4410000))
|
||||
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// Serial Mode
|
||||
word_union(SCSMR,
|
||||
uint16_t :5; //Reserved
|
||||
uint16_t SRC :3; //Sampling Control
|
||||
uint16_t CA :1; //Communication Mode.
|
||||
uint16_t CHR :1; //Character Length.
|
||||
uint16_t PE :1; //Parity Enable
|
||||
uint16_t OE :1; //Parity Mode
|
||||
uint16_t STOP :1; //Bit Stop Length
|
||||
uint16_t :1; //Reserved
|
||||
uint16_t CKS :2; //Clock Select
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial Bit Rate
|
||||
uint8_t SCBRR; //sBit Rate Setting
|
||||
pad(0x3);
|
||||
|
||||
// Serial Control Register
|
||||
word_union(SCSCR,
|
||||
uint16_t :4; //Reserved
|
||||
uint16_t TSIE :1; //Transmit Data Stop Interrupt Enable
|
||||
uint16_t ERIE :1; //Receive Error Interrupt Enable
|
||||
uint16_t BRIE :1; //Break Interrupt Enable
|
||||
uint16_t DRIE :1; //Receive Data Ready Interrupt Enable
|
||||
uint16_t TIE :1; //Transmit Interrupt Enable
|
||||
uint16_t RIE :1; //Receive Interrupt Enable
|
||||
uint16_t TE :1; //Transmit Enable
|
||||
uint16_t RE :1; //Receive Mode
|
||||
uint16_t :2; //Reserved
|
||||
uint16_t CKE :2; //Clock Enable
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Transmit Data Stop Register
|
||||
uint8_t SCTDSR; // Number of transmit data bytes
|
||||
pad(0x3);
|
||||
|
||||
// FIFO Error Count Register
|
||||
word_union(SCFER,
|
||||
uint16_t :2; //Reserved
|
||||
uint16_t PER :6; //Parity Error Count
|
||||
uint16_t :2; //Reserved
|
||||
uint16_t FER :6; //Framing Error Count
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Serial Status Register
|
||||
word_union(SCSSRR,
|
||||
uint16_t :6;
|
||||
uint16_t ORER :1; //Overrun Error
|
||||
uint16_t TSF :1; //Transmit Data Stop
|
||||
uint16_t ER :1; //Receive Error
|
||||
uint16_t TEND :1; //Transmit End
|
||||
uint16_t TDFE :1; //Transmit FIFO Data Empty
|
||||
uint16_t BRK :1; //Break Detect
|
||||
uint16_t FER :1; //Framing Error
|
||||
uint16_t PER :1; //Parity Error
|
||||
uint16_t RDF :1; //Receive FIFO Data Full
|
||||
uint16_t DR :1; //Receive Data Ready
|
||||
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// FIFO Control Register
|
||||
word_union(SCFCR,
|
||||
uint16_t TSE :1; //Transmit Data Stop Enable
|
||||
uint16_t TCRST :1; //Transmit Count Reset
|
||||
uint16_t :3; //Reserved
|
||||
uint16_t RSTRG :3; //RTS Output Active Trigger
|
||||
uint16_t RTRG :2; //Receive FIFO Data Trigger
|
||||
uint16_t TTRG :2; //Transmit FIFO Data Trigger
|
||||
uint16_t MCE :1; //Modem Control Enable
|
||||
uint16_t TFRST :1; //Transmit FIFO Data Register Reset
|
||||
uint16_t RFRST :1; //Receive FIFO Data Register Reset
|
||||
uint16_t LOOP :1; //Loopback Test
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// FIFO Data Count Register
|
||||
word_union(SCFDR,
|
||||
uint16_t :1; //Reserved
|
||||
uint16_t T :7; //Number of Untransmitted Bytes in Transmit FIFO
|
||||
uint16_t :1; //Reserved
|
||||
uint16_t R :7; //Number of Received Bytes in Receive FIFO
|
||||
);
|
||||
pad(0x2);
|
||||
|
||||
// Transmit FIFO data Register
|
||||
uint8_t SCFTDR; // Serial Transmit Data FIFO (64 Bytes-long)
|
||||
pad(0x3);
|
||||
|
||||
// Transmit FIFO data Register
|
||||
uint8_t SCFRDR; // Serial Receive Data FIFO (64 Bytes-long)
|
||||
} GPACKED(4) sh7705_scif_t;
|
||||
|
||||
#define SH7705_SCIF (*((sh7705_scif_t *)0xa4410000))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GINT_MPU_SCIF */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
//---
|
||||
// gint:mpu:wdt - Watchdog Timer
|
||||
//---
|
||||
|
||||
#ifndef GINT_MPU_WDT
|
||||
#define GINT_MPU_WDT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <gint/defs/attributes.h>
|
||||
#include <gint/defs/types.h>
|
||||
|
||||
|
||||
//---
|
||||
// SH7705 WatchDog Timer. Refer to:
|
||||
// "Renesas SH7705 Group Hardware Manual"
|
||||
// Section 10: "WatchDog Timer (WDT)"
|
||||
//---
|
||||
|
||||
/* sh7705_wdt_t - Watch Dog Timer */
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
/* WDT registers are unique in access size; reads are performed with 8-bit
|
||||
accesses, but writes are performed with 16-bit accesses. */
|
||||
|
||||
union {
|
||||
uint8_t READ;
|
||||
uint16_t WRITE;
|
||||
} WTCNT;
|
||||
|
||||
union {
|
||||
byte_union(READ,
|
||||
uint8_t TME :1; /* ... description of TME */
|
||||
uint8_t WTIT :1; /* ... description of WT/IT */
|
||||
uint8_t RSTS :1; /* ... description of RSTS */
|
||||
uint8_t WOVF :1; /* ... description of WOVF */
|
||||
uint8_t IOVF :1; /* ... description of IOVF */
|
||||
uint8_t CKS :3; /* ... description of CKS */
|
||||
);
|
||||
uint16_t WRITE;
|
||||
} WTCSR;
|
||||
|
||||
} sh7705_wdt_t;
|
||||
|
||||
|
||||
#define SH7705_WDT (*((sh7705_wdt_t *)0xFFFFFF84))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GINT_MPU_WDT */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
//---
|
||||
// gint:serial - Serial operation
|
||||
//---
|
||||
|
||||
#ifndef GINT_SERIAL
|
||||
#define GINT_SERIAL
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <gint/mpu/scif.h>
|
||||
#include <gint/mpu/pfc.h>
|
||||
#include <gint/hardware.h>
|
||||
#include <gint/defs/types.h>
|
||||
#include <gint/defs/call.h>
|
||||
|
||||
|
||||
// Prototypes of functions expected to appear in the serial module
|
||||
// aims at reproducing the OS syscalls
|
||||
|
||||
int gint_serial_read_one_byte(unsigned char *dest);
|
||||
|
||||
int gint_serial_write_one_byte(unsigned char byte);
|
||||
|
||||
int gint_serial_write_bytes(unsigned char *src, int size);
|
||||
|
||||
int gint_serial_clear_receive_buffer(void);
|
||||
|
||||
int gint_serial_clear_transmit_buffer(void);
|
||||
|
||||
int gint_serial_open(unsigned char *conf);
|
||||
|
||||
int gint_serial_close(int mode);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GINT_SERIAL */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
{
|
||||
"configurations": [
|
||||
{
|
||||
"name": "linux-gcc-x64",
|
||||
"includePath": [
|
||||
"${workspaceFolder}/**"
|
||||
],
|
||||
"compilerPath": "/usr/bin/gcc",
|
||||
"cStandard": "${default}",
|
||||
"cppStandard": "${default}",
|
||||
"intelliSenseMode": "linux-gcc-x64",
|
||||
"compilerArgs": [
|
||||
""
|
||||
]
|
||||
}
|
||||
],
|
||||
"version": 4
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
{
|
||||
"version": "0.2.0",
|
||||
"configurations": [
|
||||
{
|
||||
"name": "C/C++ Runner: Debug Session",
|
||||
"type": "cppdbg",
|
||||
"request": "launch",
|
||||
"args": [],
|
||||
"stopAtEntry": false,
|
||||
"externalConsole": false,
|
||||
"cwd": "/home/sylvain/.local/share/giteapc/Slyvtt/gint/src/cpg",
|
||||
"program": "/home/sylvain/.local/share/giteapc/Slyvtt/gint/src/cpg/build/Debug/outDebug",
|
||||
"MIMode": "gdb",
|
||||
"miDebuggerPath": "gdb",
|
||||
"setupCommands": [
|
||||
{
|
||||
"description": "Enable pretty-printing for gdb",
|
||||
"text": "-enable-pretty-printing",
|
||||
"ignoreFailures": true
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
{
|
||||
"C_Cpp_Runner.cCompilerPath": "gcc",
|
||||
"C_Cpp_Runner.cppCompilerPath": "g++",
|
||||
"C_Cpp_Runner.debuggerPath": "gdb",
|
||||
"C_Cpp_Runner.cStandard": "",
|
||||
"C_Cpp_Runner.cppStandard": "",
|
||||
"C_Cpp_Runner.msvcBatchPath": "C:/Program Files/Microsoft Visual Studio/VR_NR/Community/VC/Auxiliary/Build/vcvarsall.bat",
|
||||
"C_Cpp_Runner.useMsvc": false,
|
||||
"C_Cpp_Runner.warnings": [
|
||||
"-Wall",
|
||||
"-Wextra",
|
||||
"-Wpedantic",
|
||||
"-Wshadow",
|
||||
"-Wformat=2",
|
||||
"-Wconversion",
|
||||
"-Wnull-dereference",
|
||||
"-Wsign-conversion"
|
||||
],
|
||||
"C_Cpp_Runner.enableWarnings": true,
|
||||
"C_Cpp_Runner.warningsAsError": false,
|
||||
"C_Cpp_Runner.compilerArgs": [],
|
||||
"C_Cpp_Runner.linkerArgs": [],
|
||||
"C_Cpp_Runner.includePaths": [],
|
||||
"C_Cpp_Runner.includeSearch": [
|
||||
"*",
|
||||
"**/*"
|
||||
],
|
||||
"C_Cpp_Runner.excludeSearch": [
|
||||
"**/build",
|
||||
"**/build/**",
|
||||
"**/.*",
|
||||
"**/.*/**",
|
||||
"**/.vscode",
|
||||
"**/.vscode/**"
|
||||
]
|
||||
}
|
||||
|
|
@ -26,11 +26,9 @@ const clock_frequency_t *clock_freq(void)
|
|||
// SH7705 Clock signals
|
||||
//---
|
||||
|
||||
#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
|
||||
#define CPG SH7705_CPG
|
||||
|
||||
void sh7705_probe(void)
|
||||
static void sh7705_probe(void)
|
||||
{
|
||||
|
||||
/* According to Sentaro21 in the sources of Ftune 1.0.1, the clock mode
|
||||
is thought to be 5, which means that:
|
||||
- CPG input is XTAL (14.745'600 MHz)
|
||||
|
|
@ -41,11 +39,13 @@ void sh7705_probe(void)
|
|||
int ckio = xtal * pll2;
|
||||
|
||||
/* This signal is multiplied by the PLL1 circuit */
|
||||
int pll1 = CPG.FRQCR.STC + 1;
|
||||
int pll1 = SH7705_CPG.FRQCR.STC + 1;
|
||||
|
||||
int base = ckio * pll1;
|
||||
|
||||
/* Iphi and Pphi have dividers (Bphi is always equal to CKIO) */
|
||||
int idiv = CPG.FRQCR.IFC;
|
||||
int pdiv = CPG.FRQCR.PFC;
|
||||
int idiv = SH7705_CPG.FRQCR.IFC;
|
||||
int pdiv = SH7705_CPG.FRQCR.PFC;
|
||||
|
||||
/* Fill in the setting structure */
|
||||
freq.PLL1 = pll1;
|
||||
|
|
@ -59,43 +59,44 @@ void sh7705_probe(void)
|
|||
|
||||
/* Exchange the setting values 2 and 3 (corresponding to /3 and /4)
|
||||
This means that /1, /2, /4 are now 0, 1, 2, which is perfect for a
|
||||
quick bit shift */
|
||||
idiv = idiv ^ (idiv >> 1);
|
||||
pdiv = pdiv ^ (pdiv >> 1);
|
||||
quick bit shift*/
|
||||
//idiv = idiv ^ (idiv >> 1);
|
||||
//pdiv = pdiv ^ (pdiv >> 1);
|
||||
|
||||
freq.CKIO_f = ckio;
|
||||
freq.Bphi_f = ckio;
|
||||
freq.Iphi_f = (idiv == 3) ? ckio_3 : ckio >> idiv;
|
||||
freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
|
||||
//freq.Iphi_f = (idiv == 3) ? ckio_3 : ckio >> idiv;
|
||||
//freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
|
||||
|
||||
freq.Iphi_f = base / freq.Iphi_div;
|
||||
freq.Pphi_f = base / freq.Pphi_div;
|
||||
|
||||
|
||||
}
|
||||
|
||||
#undef CPG
|
||||
#endif /* FX9860G and platform-agnostic */
|
||||
|
||||
//---
|
||||
// SH7305 clock signals
|
||||
//---
|
||||
|
||||
#define CPG SH7305_CPG
|
||||
|
||||
static void sh7305_probe(void)
|
||||
{
|
||||
/* The meaning of the PLL setting on SH7305 differs from the
|
||||
documentation of SH7224; the value must not be doubled. */
|
||||
int pll = CPG.FRQCR.STC + 1;
|
||||
int pll = SH7305_CPG.FRQCR.STC + 1;
|
||||
freq.PLL = pll;
|
||||
|
||||
/* The FLL ratio is the value of the setting, halved if SELXM=1 */
|
||||
int fll = CPG.FLLFRQ.FLF;
|
||||
if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
|
||||
int fll = SH7305_CPG.FLLFRQ.FLF;
|
||||
if(SH7305_CPG.FLLFRQ.SELXM == 1) fll >>= 1;
|
||||
freq.FLL = fll;
|
||||
|
||||
/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
|
||||
the SH7305 it is 1 / (2^setting + 1). */
|
||||
|
||||
int divb = CPG.FRQCR.BFC;
|
||||
int divi = CPG.FRQCR.IFC;
|
||||
int divp = CPG.FRQCR.P1FC;
|
||||
int divb = SH7305_CPG.FRQCR.BFC;
|
||||
int divi = SH7305_CPG.FRQCR.IFC;
|
||||
int divp = SH7305_CPG.FRQCR.P1FC;
|
||||
|
||||
freq.Bphi_div = 1 << (divb + 1);
|
||||
freq.Iphi_div = 1 << (divi + 1);
|
||||
|
|
@ -103,8 +104,8 @@ static void sh7305_probe(void)
|
|||
|
||||
/* Deduce the input frequency of divider 1 */
|
||||
int base = 32768;
|
||||
if(CPG.PLLCR.FLLE) base *= fll;
|
||||
if(CPG.PLLCR.PLLE) base *= pll;
|
||||
if(SH7305_CPG.PLLCR.FLLE) base *= fll;
|
||||
if(SH7305_CPG.PLLCR.PLLE) base *= pll;
|
||||
|
||||
/* And the frequency of all other input clocks */
|
||||
freq.RTCCLK_f = 32768;
|
||||
|
|
@ -113,9 +114,6 @@ static void sh7305_probe(void)
|
|||
freq.Pphi_f = base >> (divp + 1);
|
||||
}
|
||||
|
||||
#undef CPG
|
||||
|
||||
|
||||
//---
|
||||
// Initialization
|
||||
//---
|
||||
|
|
@ -124,10 +122,14 @@ void cpg_compute_freq(void)
|
|||
{
|
||||
/* This avoids warnings about sh7705_probe() being undefined when
|
||||
building for fxcg50 */
|
||||
|
||||
/*
|
||||
#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
|
||||
isSH3() ? sh7705_probe() :
|
||||
#endif
|
||||
sh7305_probe();
|
||||
*/
|
||||
isSH3() ? sh7705_probe() : sh7305_probe();
|
||||
}
|
||||
|
||||
static void configure(void)
|
||||
|
|
@ -149,16 +151,16 @@ static void hsave(cpg_state_t *s)
|
|||
{
|
||||
if(isSH4()) {
|
||||
s->SSCGCR = SH7305_CPG.SSCGCR.lword;
|
||||
cpg_get_overclock_setting(&s->speed);
|
||||
}
|
||||
cpg_get_overclock_setting(&s->speed);
|
||||
}
|
||||
|
||||
static void hrestore(cpg_state_t const *s)
|
||||
{
|
||||
if(isSH4()) {
|
||||
SH7305_CPG.SSCGCR.lword = s->SSCGCR;
|
||||
cpg_set_overclock_setting(&s->speed);
|
||||
}
|
||||
cpg_set_overclock_setting(&s->speed);
|
||||
}
|
||||
|
||||
gint_driver_t drv_cpg = {
|
||||
|
|
|
|||
|
|
@ -14,10 +14,17 @@
|
|||
#include <gint/hardware.h>
|
||||
#include <gint/mpu/cpg.h>
|
||||
#include <gint/mpu/bsc.h>
|
||||
#include <gint/mpu/wdt.h>
|
||||
|
||||
/*
|
||||
#define CPG SH7305_CPG
|
||||
#define BSC SH7305_BSC
|
||||
|
||||
#define SH7705_CPG SH7705_CPG
|
||||
#define SH7705_BSC SH7705_BSC
|
||||
#define SH7705_WDT SH7705_WDT
|
||||
*/
|
||||
|
||||
//---
|
||||
// Low-level clock speed access
|
||||
//---
|
||||
|
|
@ -25,68 +32,133 @@
|
|||
#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
|
||||
#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
|
||||
|
||||
void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
|
||||
{
|
||||
if(!isSH4())
|
||||
return;
|
||||
|
||||
s->FLLFRQ = CPG.FLLFRQ.lword;
|
||||
s->FRQCR = CPG.FRQCR.lword;
|
||||
|
||||
s->CS0BCR = BSC.CS0BCR.lword;
|
||||
s->CS0WCR = BSC.CS0WCR.lword;
|
||||
s->CS2BCR = BSC.CS2BCR.lword;
|
||||
s->CS2WCR = BSC.CS2WCR.lword;
|
||||
s->CS3BCR = BSC.CS3BCR.lword;
|
||||
s->CS3WCR = BSC.CS3WCR.lword;
|
||||
s->CS5aBCR = BSC.CS5ABCR.lword;
|
||||
s->CS5aWCR = BSC.CS5AWCR.lword;
|
||||
}
|
||||
|
||||
void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
|
||||
{
|
||||
if(!isSH4())
|
||||
return;
|
||||
|
||||
BSC.CS0WCR.WR = 11; /* 18 cycles */
|
||||
|
||||
CPG.FLLFRQ.lword = s->FLLFRQ;
|
||||
CPG.FRQCR.lword = s->FRQCR;
|
||||
CPG.FRQCR.KICK = 1;
|
||||
while(CPG.LSTATS != 0) {}
|
||||
|
||||
BSC.CS0BCR.lword = s->CS0BCR;
|
||||
BSC.CS0WCR.lword = s->CS0WCR;
|
||||
BSC.CS2BCR.lword = s->CS2BCR;
|
||||
BSC.CS2WCR.lword = s->CS2WCR;
|
||||
BSC.CS3BCR.lword = s->CS3BCR;
|
||||
BSC.CS3WCR.lword = s->CS3WCR;
|
||||
|
||||
if(BSC.CS3WCR.A3CL == 1)
|
||||
*SDMR3_CL2 = 0;
|
||||
else
|
||||
*SDMR3_CL3 = 0;
|
||||
|
||||
BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||
BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||
}
|
||||
|
||||
//---
|
||||
// Predefined clock speeds
|
||||
//---
|
||||
|
||||
#ifdef FXCG50
|
||||
// for SH4 based calculators
|
||||
#define SH4_PLL_32x 0b011111
|
||||
#define SH4_PLL_26x 0b011001
|
||||
#define SH4_PLL_16x 0b001111
|
||||
#define SH4_DIV_2 0
|
||||
#define SH4_DIV_4 1
|
||||
#define SH4_DIV_8 2
|
||||
#define SH4_DIV_16 3
|
||||
#define SH4_DIV_32 4
|
||||
|
||||
#define PLL_32x 0b011111
|
||||
#define PLL_26x 0b011001
|
||||
#define PLL_16x 0b001111
|
||||
#define DIV_2 0
|
||||
#define DIV_4 1
|
||||
#define DIV_8 2
|
||||
#define DIV_16 3
|
||||
#define DIV_32 4
|
||||
// for SH3 based calculators
|
||||
#define SH3_PLL_1x 0 //0b0000 // x1
|
||||
#define SH3_PLL_2x 1 //0b0001 // x2
|
||||
#define SH3_PLL_3x 2 //0b0010 // x3
|
||||
#define SH3_PLL_4x 3 //0b0011 // x4
|
||||
|
||||
static struct cpg_overclock_setting settings_cg50[5] = {
|
||||
#define SH3_DIV_1 0 //0b0000 // 1/1
|
||||
#define SH3_DIV_2 1 //0b0001 // 1/2
|
||||
#define SH3_DIV_3 2 //0b0010 // 1/3
|
||||
#define SH3_DIV_4 3 //0b0011 // 1/4
|
||||
|
||||
|
||||
|
||||
static struct cpg_overclock_setting save_parameters_at_start = {0};
|
||||
static bool is_initial_state_saved = false;
|
||||
|
||||
|
||||
void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
|
||||
{
|
||||
if(isSH3())
|
||||
{
|
||||
s->FLLFRQ = 0xFFFFFFF; // not used for SH3 MPUs
|
||||
s->FRQCR = (uint32_t) SH7705_CPG.FRQCR.word;
|
||||
|
||||
s->CS0BCR = SH7705_BSC.CS0BCR.lword;
|
||||
s->CS0WCR = SH7705_BSC.CS0WCR.lword;
|
||||
s->CS2BCR = SH7705_BSC.CS2BCR.lword;
|
||||
s->CS2WCR = SH7705_BSC.CS2WCR.lword;
|
||||
s->CS3BCR = SH7705_BSC.CS3BCR.lword;
|
||||
s->CS3WCR = SH7705_BSC.CS3WCR.lword;
|
||||
s->CS5aBCR = SH7705_BSC.CS5ABCR.lword;
|
||||
s->CS5aWCR = SH7705_BSC.CS5AWCR.lword;
|
||||
}
|
||||
|
||||
if(isSH4())
|
||||
{
|
||||
s->FLLFRQ = SH7305_CPG.FLLFRQ.lword;
|
||||
s->FRQCR = SH7305_CPG.FRQCR.lword;
|
||||
|
||||
s->CS0BCR = SH7305_BSC.CS0BCR.lword;
|
||||
s->CS0WCR = SH7305_BSC.CS0WCR.lword;
|
||||
s->CS2BCR = SH7305_BSC.CS2BCR.lword;
|
||||
s->CS2WCR = SH7305_BSC.CS2WCR.lword;
|
||||
s->CS3BCR = SH7305_BSC.CS3BCR.lword;
|
||||
s->CS3WCR = SH7305_BSC.CS3WCR.lword;
|
||||
s->CS5aBCR = SH7305_BSC.CS5ABCR.lword;
|
||||
s->CS5aWCR = SH7305_BSC.CS5AWCR.lword;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
|
||||
{
|
||||
if(isSH3())
|
||||
{
|
||||
SH7705_WDT.WTCNT.WRITE = 0;
|
||||
SH7705_WDT.WTCSR.WRITE = 0x65;
|
||||
SH7705_CPG.FRQCR.word = (uint16_t) (0x1000 | ((uint16_t) s->FRQCR));
|
||||
SH7705_BSC.CS0BCR.lword = s->CS0BCR;
|
||||
SH7705_BSC.CS0WCR.lword = s->CS0WCR;
|
||||
SH7705_BSC.CS2BCR.lword = s->CS2BCR;
|
||||
SH7705_BSC.CS2WCR.lword = s->CS2WCR;
|
||||
SH7705_BSC.CS3BCR.lword = s->CS3BCR;
|
||||
SH7705_BSC.CS3WCR.lword = s->CS3WCR;
|
||||
SH7705_BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||
SH7705_BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||
}
|
||||
|
||||
if(isSH4())
|
||||
{
|
||||
SH7305_BSC.CS0WCR.WR = 11; /* 18 cycles */
|
||||
|
||||
SH7305_CPG.FLLFRQ.lword = s->FLLFRQ;
|
||||
SH7305_CPG.FRQCR.lword = s->FRQCR;
|
||||
SH7305_CPG.FRQCR.KICK = 1;
|
||||
while(SH7305_CPG.LSTATS != 0) {}
|
||||
|
||||
SH7305_BSC.CS0BCR.lword = s->CS0BCR;
|
||||
SH7305_BSC.CS0WCR.lword = s->CS0WCR;
|
||||
SH7305_BSC.CS2BCR.lword = s->CS2BCR;
|
||||
SH7305_BSC.CS2WCR.lword = s->CS2WCR;
|
||||
SH7305_BSC.CS3BCR.lword = s->CS3BCR;
|
||||
SH7305_BSC.CS3WCR.lword = s->CS3WCR;
|
||||
|
||||
if(SH7305_BSC.CS3WCR.A3CL == 1)
|
||||
*SDMR3_CL2 = 0;
|
||||
else
|
||||
*SDMR3_CL3 = 0;
|
||||
|
||||
SH7305_BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||
SH7305_BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void clock_save_state(void)
|
||||
{
|
||||
cpg_get_overclock_setting( &save_parameters_at_start );
|
||||
is_initial_state_saved = true;
|
||||
}
|
||||
|
||||
void clock_restore_state(void)
|
||||
{
|
||||
if(is_initial_state_saved==true)
|
||||
cpg_set_overclock_setting( &save_parameters_at_start );
|
||||
}
|
||||
|
||||
|
||||
/*settings for the fxcg50 / G90+E*/
|
||||
static struct cpg_overclock_setting settings_fxcg50[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = 0x0F011112,
|
||||
|
|
@ -100,7 +172,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
|
|||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -111,7 +183,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
|
|||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -122,7 +194,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
|
|||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV_16,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -133,7 +205,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
|
|||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -144,7 +216,8 @@ static struct cpg_overclock_setting settings_cg50[5] = {
|
|||
.CS5aWCR = 0x000203C1 },
|
||||
};
|
||||
|
||||
static struct cpg_overclock_setting settings_cg20[5] = {
|
||||
/*settings for the prizm fxcg10/20*/
|
||||
static struct cpg_overclock_setting settings_prizm[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = 0x0F102203,
|
||||
|
|
@ -158,7 +231,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_8<<20)+(DIV_16<<12)+(DIV_16<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_16<<12)+(SH4_DIV_16<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -169,7 +242,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x24900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -180,7 +253,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x44900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -191,7 +264,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_16,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x34900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -202,38 +275,243 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
};
|
||||
|
||||
/*settings for the fx9860G SH3 based*/
|
||||
static struct cpg_overclock_setting settings_fx9860g_sh3[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
|
||||
.FRQCR = 0x1001,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
|
||||
.FRQCR = (SH3_PLL_2x<<8)+(SH3_DIV_1<<4)+SH3_DIV_2,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
|
||||
.FRQCR = (SH3_PLL_3x<<8)+(SH3_DIV_1<<4)+SH3_DIV_3,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
|
||||
.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
|
||||
.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000000C0,
|
||||
.CS2WCR = 0x000100C0,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
};
|
||||
|
||||
/*settings for the fx9860GII*/
|
||||
static struct cpg_overclock_setting settings_fx9860g_sh4[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = 0x0F202203,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000005C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x24920200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000003C0,
|
||||
.CS2WCR = 0x000302C0,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
};
|
||||
|
||||
/*settings for the fx9860GII-2 / G35+EII*/
|
||||
static struct cpg_overclock_setting settings_g35pe2[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = 0x0F202203,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000005C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00031340 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00031340 },
|
||||
};
|
||||
|
||||
static struct cpg_overclock_setting *get_settings(void)
|
||||
{
|
||||
if(gint[HWCALC] == HWCALC_FXCG50)
|
||||
return settings_cg50;
|
||||
return settings_fxcg50;
|
||||
if(gint[HWCALC] == HWCALC_PRIZM)
|
||||
return settings_cg20;
|
||||
return settings_prizm;
|
||||
if(gint[HWCALC] == HWCALC_G35PE2)
|
||||
return settings_g35pe2;
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH4)
|
||||
return settings_fx9860g_sh4;
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH3)
|
||||
return settings_fx9860g_sh3;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int clock_get_speed(void)
|
||||
{
|
||||
struct cpg_overclock_setting *settings = get_settings();
|
||||
if(!settings)
|
||||
return CLOCK_SPEED_UNKNOWN;
|
||||
struct cpg_overclock_setting *settings = get_settings();
|
||||
if(!settings)
|
||||
return CLOCK_ERROR;
|
||||
|
||||
if(isSH3())
|
||||
{
|
||||
for(int i = 0; i < 5; i++) {
|
||||
struct cpg_overclock_setting *s = &settings[i];
|
||||
|
||||
if(CPG.FLLFRQ.lword == s->FLLFRQ
|
||||
&& CPG.FRQCR.lword == s->FRQCR
|
||||
&& BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
if(SH7705_CPG.FRQCR.word == (uint16_t) (s->FRQCR | 0x1000) // FRQCR is a uint16_t for SH3
|
||||
&& SH7705_BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& SH7705_BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& SH7705_BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& SH7705_BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& SH7705_BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& SH7705_BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& SH7705_BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& SH7705_BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
return CLOCK_SPEED_F1 + i;
|
||||
}
|
||||
}
|
||||
|
||||
if(isSH4())
|
||||
{
|
||||
for(int i = 0; i < 5; i++) {
|
||||
struct cpg_overclock_setting *s = &settings[i];
|
||||
|
||||
return CLOCK_SPEED_UNKNOWN;
|
||||
if(SH7305_CPG.FLLFRQ.lword == s->FLLFRQ
|
||||
&& SH7305_CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4
|
||||
&& SH7305_BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& SH7305_BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& SH7305_BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& SH7305_BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& SH7305_BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& SH7305_BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& SH7305_BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& SH7305_BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
return CLOCK_SPEED_F1 + i;
|
||||
}
|
||||
}
|
||||
|
||||
clock_save_state();
|
||||
return CLOCK_SPEED_UNKNOWN;
|
||||
}
|
||||
|
||||
void clock_set_speed(int level)
|
||||
|
|
@ -268,6 +546,4 @@ void clock_set_speed(int level)
|
|||
timer_rescale(old_Pphi, new_Pphi);
|
||||
|
||||
cpu_atomic_end();
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
//---
|
||||
// gint:serial - Serial operation
|
||||
//---
|
||||
|
||||
#include <gint/serial.h>
|
||||
|
||||
#define SCIF SH7305_SCIF
|
||||
#define PFC SH7305_PFC
|
||||
|
||||
|
||||
int gint_serial_read_one_byte(unsigned char *dest)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_write_one_byte(unsigned char byte)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_write_bytes(unsigned char *src, int size)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_clear_receive_buffer(void)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_clear_transmit_buffer(void)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_open(unsigned char *conf)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_close(int mode)
|
||||
{
|
||||
|
||||
};
|
||||
Loading…
Reference in New Issue